Xilinx KCU105 User Manual page 37

• During bridge register initialization:
Bridge base low (0x210) is programmed to (BAR0 + 0x8000).
°
Bridge Control register (0x208) is programmed to set the bridge size and enable
°
translation.
• After bridge translation has been enabled, the ingress registers can be accessed with
Bridge Base + 0x800.
Expresso DMA
Key features of Expresso DMA are:
• High-Performance Scatter Gather DMA, designed to achieve full bandwidth of AXI and
PCIe
• Separate source and destination scatter-gather queues with separate source and
destination DMA completion Status queues
• DMA channels merge the source and destination scatter gather information
AXI Block RAM Controller
The AXI block RAM controller provides block RAM with an AXI4 memory-mapped interface.
This behaves as a register file in this design to which BAR-mapped transactions are
targeted.
See LogiCORE IP AXI Block RAM (BRAM) Controller Product Guide (PG078)
details.
AXI Interconnect
The AXI Interconnect is used to connect the various IPs together in a memory-mapped
system. The interconnect is responsible for:
• Converting AXI3 transactions from AXI-PCIe bridge into AXI4 transactions for various
slaves
• Decoding address to target appropriate slave
See LogiCORE IP AXI Interconnect Product Guide (PG059)
PCI Express Control Plane TRD
UG918 (v2017.2) July 18, 2017
Chapter 5: Targeted Reference Design Details and Modifications
www.xilinx.com
[Ref 6]
[Ref 7] for more details.
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