Table of Contents
Advertisement
Signal Description
Here is the detailed description of each signal passing through the FX18-60S connector.
Pin No.
Signal
I/O
Description
Display Interface
140
DDP_HPD
I
Display Port Hot Plug Detect. Active High
139
DDI1_TXP2
Display Port Data Channels
138
DDI1_TXN2
136
DDI1_TXP3
135
DDI1_TXN3
110
DDI1_TXP0
109
DDI1_TXN0
107
DDI1_TXP1
106
DDI1_TXN1
104
DDI_AUXP
Display Port Auxiliary Channel
103
DDI_AUXN
PCIe Interface
132
PCIe_RST
I
126
PCIE-TXP3
O
PCI Express Differential Transmit Pair Signals
125
PCIE-TXN3
O
122
PCIE-TXP2
O
121
PCIE-TXN2
O
118
PCIE-TXP1
O
117
PCIE-TXN1
O
110
PCIE-TXP0
O
109
PCIE-TXN0
O
111
PCI_E_WAKE
I
Wake Indicator from PCI-E PHY Device
96
PCIE_CLK_P
O
100-MHz PCIe 3.0 specification compliant differential output clocks to
PCIe devices
97
PCIE_CLK_N
O
Chapter 2 Hardware Installation
Chapter 5 Ports and Connectors
Chapter 5
94
PCIE-RXP3
93
PCIE-RXN3
90
PCIE-RXP2
89
PCIE-RXN2
86
PCIE-RXP1
85
PCIE-RXN1
82
PCIE-RXP0
81
PCIE-RXN0
I2C/GPIO interface (5pins – 2 used for LAN Control)
133
GPIO
129
I2C_DATA_LAN
128
I2C_CLK_LAN
101
I2C1_DATA1
100
I2C1_CLK
LAN Control Interface (5 pins)
130
LAN_DISABLE
129
I2C2_DATA_LAN
128
I2C2_CLK_LAN
131
SLEEP_S3
111
PCIE_WAKE
32
I
PCI Express Differential Receive Pair Signals
I
I
I
I
I
I
I
I/O
General purpose Input Output, 3.3V
I/O
System Management Data Link to external PHY
I/O
System Management Clock Link to external PHY
I/O
I2C bus data
O
I2C bus clock
O
It should be connected to LAN_DISABLE_N on the PHY. PCH will drive
it low to put the PHY into a low power state when functionality is not
needed.
I/O
System Management (I2C/SMBus) Data Link to external PHY
I/O
System Management (I2C/SMBus) Clock link to external PHY
O
LAN sub-system sleep control. When it is deasserted it indicates that the
PHY device must be powered. When it is asserted, power can be shut off
to the PHY device.
I
Wake Indicator from PCI-E PHY Device
www.dfi.com
Advertisement
Table of Contents
