Table 46: USP Configuration - Advanced Parameters (continued)
Field
DTR
RTS
CTS
Invert Tx Clock
Ignore DCD
Transmitter Delay
Loopback
Description
The port's Data Terminal Ready status. Possible values are:
Up - The port is physically prepared to transmit and receive
●
packets.
Down - The port is not physically prepared to transmit and
●
receive packets. This generally indicates an error condition on
the circuit.
The port's Ready To Send status. Possible values are:
Up - The port is logically prepared to transmit and receive
●
packets.
Down - The port is not logically prepared to transmit and
●
receive packets. This generally indicates an error condition
either on the device or the circuit.
The port's Clear To Send status. Possible values are:
Up - The port has successfully completed initial line signalling.
●
CTS takes place at the end of the initial line signalling process
and last for a short period of time.
Down - The port has either failed to complete initial line
●
signalling or the initial line signalling process has been
completed.
The state of the Tx clock. Possible states are:
On - The Tx clock is inverted.
●
Off - The Tx clock is not inverted.
●
The signal type monitored to determine the interface's status.
Possible values are:
On - The interface monitors DSR/CTS signals and ignores
●
DCD signals.
Off - The interface monitors DCD signals.
●
The delay between the CTS signal and the beginning of transmission.
The status of the DTE loopback. Possible values are:
On - DTE loopback is enabled, indicating a line test taking
●
place.
Off - DTE loopback is disabled, indicating normal circuit
●
operation.
USP Configuration
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Issue 5 October 2007
131