C Register Map And Reset Values; Table 51. I 2 C Register Map - ST STM8S Reference Manual

Inter-integrated circuit (I
Bits 5:0 TRISE[5:0] Maximum rise time in Fast/Standard mode (Master mode)
These bits must be programmed with the maximum SCL rise time given in the I2C bus specification,
incremented by 1.
For instance: in standard mode, the maximum allowed SCL rise time is 1000 ns.
If the value in the I2C_FREQR register = 08h, then t
must be programmed with 0x09.
(1000 ns / 125 ns = 8 + 1)
The filter value can also be added to TRISE[5:0].
If the result is not an integer, TRISE[5:0] must be programmed with the integer part, in order to
respect the t
Note: TRISE[5:0] must be configured only when the I2C is disabled (PE = 0).
2
21.7.14 I

C register map and reset values

2
Table 51. I C register map
Address Register
offset name
I2C_CR1
0x00
Reset value
I2C_CR2
0x01
Reset value
I2C_FREQR
0x02
Reset value
I2C_OARL
0x03
Reset value
I2C_OARH
0x04
Reset value
0x05
I2C_DR
0x06
Reset value
I2C_SR1
0x07
Reset value
I2C_SR2
0x08
Reset value
I2C_SR3
0x09
Reset value
I2C_ITR
0x0A
Reset value
I2C_CCRL
0x0B
Reset value
I2C_CCRH
0x0C
Reset value
I2C_TRISER
0x0D
Reset value
306/449
2
C) interface
parameter.
HIGH
7 6
NO STRETCH ENGC
0 0
SWRST -
0 0
- -
0 0
ADDMODE ADDCONF
0 0
TXE RXNE
0 0
- -
0 0
- -
0 0
- -
0 0
FS DUTY
0 0
- -
0 0
Doc ID 14587 Rev 8
= 125 ns therefore the TRISE[5:0] bits
MASTER
5 4
- -
0 0
- - POS
0 0
FREQ5 FREQ4 FREQ3
0 0
ADD[7:1]
0
- -
0 0
Reserved
DR[7:0]
0
- STOPF ADD10
0 0
WUFH - OVR
0 0
- GENCALL
0 0
- --
0 0
CCR[7:0]
0
- -
0 0
3 2 1
- - -
0 0 0
ACK STOP
0 0 0
FREQ2 FREQ1
0 0 0
- ADD[9:8]
0 0
BTF ADDR
0 0 0
AF ARLO
0 0 0
- TRA BUSY
0 0 0
-- ITBUFEN ITEVTEN
0 0 0
CCR[11:8]
0
TRISE[5:0]
0
RM0016
0
PE
0
START
0
FREQ0
0
ADD0
0
-
0
SB
0
BERR
0
MSL
0
ITERREN
0