Figure 121. Uart Example Of Synchronous Transmission; Figure 122. Uart Data Clock Timing Diagram (M=0); Figure 123. Uart Data Clock Timing Diagram (M=1) - ST STM8S Reference Manual

RM0016

Figure 121. UART example of synchronous transmission

Figure 122. UART data clock timing diagram (M=0)

Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)

Figure 123. UART data clock timing diagram (M=1)

Clock (CPOL=0, CPHA=0)
Clock (CPOL=0, CPHA=1)
Clock (CPOL=1, CPHA=0)
Clock (CPOL=1, CPHA=1)
Universal asynchronous receiver transmitter (UART)
RX
TX
UART
SCLK
Idle or preceding
Start
transmission
Data
0
Start LSB
Idle or preceding
Start
transmission
Data
0
Start LSB
Doc ID 14587 Rev 8
Data out
Data in
Synchronous device
(for example slave SPI)
Clock
M=0 (8 data bits)
1 2 3 4 5
* LBCL bit controls last data clock pulse
M=1 (9 data bits)
1 2 3 4 5
* LBCL bit controls last data clock pulse
Idle or next
Stop transmission
*
*
*
*
6 7
MSB Stop
Idle or next
Stop
transmission
*
*
*
*
8
6 7
MSB Stop
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