ST STM8A Manuals

Manuals and User Guides for ST STM8A. We have 2 ST STM8A manuals available for free PDF download: Reference Manual, Application Note

ST STM8A Reference Manual (449 pages)

Brand: ST | Category: Microcontrollers | Size: 5 MB

Table of Contents
2
Central Processing Unit (CPU)

23
- Introduction
  23
- CPU Registers
  23
  - Description of CPU Registers
    23
  - Figure 1. Programming Model
    24
  - Figure 2. Stacking Order
    25
  - Table 1. Interrupt Levels
    26
  - STM8 CPU Register Map
    27
- Global Configuration Register (CFG_GCR)
  27
Boot ROM

29
Memory and Register Map

30
- Memory Layout
  30
  - Memory Map
    30
  - Figure 3. Memory Map
    30
  - Stack Handling
    31
  - Figure 4. Default Stack Model
    31
  - Figure 5. Customized Stack Model
    32
- Register Description Abbreviations
  33
- Table 4. List of Abbreviations
  33
Flash Program Memory and Data EEPROM

34
Single Wire Interface Module (SWIM) and Debug Module (DM)

57
- Introduction
  57
- Main Features
  57
- SWIM Modes
  57
- Figure 12. SWIM Pin Connection
  57
Interrupt Controller (ITC)

58
Power Supply

72
- Figure 17. Power Supply Overview
  72
Reset (RST)

73
- Reset State" and "Under Reset" Definitions
  73
- Reset Circuit Description
  73
- Figure 18. Reset Circuit
  73
- Internal Reset Sources
  74
  - Power-On Reset (POR) and Brown-Out Reset (BOR)
    74
  - Figure 19. VDD/VDDIO Voltage Detection: POR/BOR Threshold
    74
  - Watchdog Reset
    75
  - Software Reset
    75
  - SWIM Reset
    75
  - Illegal Opcode Reset
    75
  - EMC Reset
    75
- RST Register Description
  76
  - Reset Status Register (RST_SR)
    76
- RST Register Map
  76
- Table 13. RST Register Map
  76
Clock Control (CLK)

77
Power Management

101
- General Considerations
  101
  - Clock Management for Low Consumption
    102
- Low Power Modes
  102
  - Table 20. Low Power Mode Management
    102
  - Active-Halt Modes
    103
  - Halt Mode
    103
  - Wait Mode
    103
- Additional Analog Power Controls
  104
  - Fast Flash Wakeup from Halt Mode
    104
  - Very Low Flash Consumption in Active-Halt Mode
    104
General Purpose I/O Ports (GPIO)

105
- Introduction
  105
- GPIO Main Features
  105
- Port Configuration and Usage
  106
  - Figure 24. GPIO Block Diagram
    106
  - Input Modes
    107
  - Output Modes
    107
  - Table 21. I/O Port Configuration Summary
    107
- Reset Configuration
  108
- Unused I/O Pins
  108
- Low Power Modes
  108
- Input Mode Details
  108
  - Alternate Function Input
    108
  - Table 22. Effect of Low Power Modes on GPIO Ports
    108
  - Interrupt Capability
    109
  - Analog Channels
    109
  - Schmitt Trigger
    109
- Output Mode Details
  109
- GPIO Registers
  111
Auto-Wakeup (AWU)

114
- Introduction
  114
- LSI Clock Measurement
  114
- Figure 25. AWU Block Diagram
  114
- AWU Functional Description
  115
  - AWU Operation
    115
  - Time Base Selection
    116
  - Table 25. Time Base Calculation Table
    116
  - LSI Clock Frequency Measurement
    117
- AWU Registers
  118
Beeper (BEEP)

120
- Introduction
  120
- Beeper Functional Description
  120
  - Beeper Operation
    120
  - Figure 26. Beep Block Diagram
    120
  - Beeper Calibration
    121
- Beeper Registers
  121
Independent Watchdog (IWDG)

122
- Introduction
  122
- IWDG Functional Description
  122
- Figure 27. Independent Watchdog (IWDG) Block Diagram
  122
- Table 28. Watchdog Timeout Period (LSI Clock Frequency = 128 Khz)
  123
- IWDG Registers
  124
  - Key Register (IWDG_KR)
    124
  - Prescaler Register (IWDG_PR)
    124
  - Reload Register (IWDG_RLR)
    125
  - IWDG Register Map and Reset Values
    125
  - Table 29. IWDG Register Map
    125
Window Watchdog (WWDG)

126
- Introduction
  126
- WWDG Main Features
  126
- WWDG Functional Description
  126
- Figure 28. Watchdog Block Diagram
  127
- How to Program the Watchdog Timeout
  128
- Figure 29. Approximate Timeout Duration
  128
- WWDG Low Power Modes
  129
- Table 30. Window Watchdog Timing Example
  129
- Table 31. Effect of Low Power Modes on WWDG
  129
- Figure 30. Window Watchdog Timing Diagram
  129
- Hardware Watchdog Option
  130
- Using Halt Mode with the WWDG (WWDGHALT Option)
  130
- WWDG Interrupts
  130
- WWDG Registers
  130
  - Control Register (WWDG_CR)
    130
  - Window Register (WWDG_WR)
    130
- Window Watchdog Register Map and Reset Values
  131
- Table 32. WWDG Register Map and Reset Values
  131
Timer Overview

132
16-Bit Advanced Control Timer (TIM1)

136
16-Bit General Purpose Timers (TIM2, TIM3, TIM5)

216
- Introduction
  216
- TIM2/TIM3 Main Features
  216
- TIM5 Main Features
  217
- TIM2/TIM3/TIM5 Functional Description
  217
  - Figure 82. TIM2/TIM3 Block Diagram
    217
  - Figure 84. Time Base Unit
    217
  - Figure 83. TIM5 Block Diagram
    218
  - Time Base Unit
    218
  - Clock/Trigger Controller
    219
  - Capture/Compare Channels
    220
  - Figure 85. Input Stage Block Diagram
    220
  - Figure 86. Input Stage of TIM 2 Channel 1
    220
- TIM2/TIM3/TIM5 Interrupts
  221
- Figure 87. Output Stage
  221
- Figure 88. Output Stage of Channel 1
  221
- TIM2/TIM3/TIM5 Registers
  223
8-Bit Basic Timer (TIM4, TIM6)

243
- Introduction
  243
- Figure 89. TIM4 Block Diagram
  243
- Figure 90. TIM6 Block Diagram
  243
- TIM4 Main Features
  244
- TIM6 Main Features
  244
- TIM4/TIM6 Interrupts
  244
- TIM4/TIM6 Clock Selection
  244
- TIM4/TIM6 Registers
  245
  - Control Register 1 (Timx_Cr1)
    245
  - Control Register 2 (TIM6_CR2)
    246
  - Slave Mode Control Register (TIM6_SMCR)
    246
  - Interrupt Enable Register (Timx_Ier)
    247
  - Status Register 1 (Timx_Sr)
    248
  - Event Generation Register (Timx_Egr)
    248
  - Counter (Timx_Cntr)
    249
  - Prescaler Register (Timx_Pscr)
    250
  - Auto-Reload Register (Timx_Arr)
    250
  - TIM4/TIM6 Register Map and Reset Values
    251
  - Table 43. TIM4 Register Map
    251
  - Table 44. TIM6 Register Map
    251
Serial Peripheral Interface (SPI)

253
Inter-Integrated Circuit (I 2 C) Interface

278
Universal Asynchronous Receiver Transmitter (UART)

307
Controller Area Network (Becan)

362
- Introduction
  362
- Becan Main Features
  362
- Becan General Description
  363
  - CAN 2.0B Active Core
    363
  - Control, Status and Configuration Registers
    363
  - Figure 139. CAN Network Topology
    363
  - Tx Mailboxes
    364
  - Acceptance Filters
    364
  - Figure 140. Becan Block Diagram
    364
- Operating Modes
  365
  - Initialization Mode
    365
  - Figure 141. Becan Operating Modes
    365
  - Normal Mode
    366
  - Sleep Mode (Low Power)
    366
  - Time Triggered Communication Mode
    366
- Test Modes
  367
  - Silent Mode
    367
  - Loop Back Mode
    367
  - Figure 142. Becan in Silent Mode
    367
  - Figure 143. Becan in Loop Back Mode
    367
  - Loop Back Combined with Silent Mode
    368
- Functional Description
  368
- Interrupts
  383
- Figure 155. Event Flags and Interrupt Generation
  383
- Register Access Protection
  384
- Clock System
  384
- Becan Low Power Modes
  384
- Table 67. Becan Behavior in Low Power Modes
  384
- Becan Registers
  385
- CAN Register Map
  407
Analog/Digital Converter (ADC)

411
- Introduction
  411
- ADC Main Features
  411
- ADC Extended Features
  411
- Figure 158. ADC1 Block Diagram
  412
- Figure 159. ADC2 Block Diagram
  413
- ADC Pins
  414
- ADC Functional Description
  414
  - ADC On-Off Control
    414
  - ADC Clock
    414
  - Channel Selection
    415
  - Conversion Modes
    415
  - Overrun Flag
    416
  - Analog Watchdog
    417
  - Figure 160. Analog Watchdog Guarded Area
    417
  - Conversion on External Trigger
    418
  - Analog Zooming
    418
  - Timing Diagram
    418
  - Figure 161. Timing Diagram in Single Mode (CONT = 0)
    419
  - Figure 162. Timing Diagram in Continuous Mode (CONT = 1)
    419
- ADC Low Power Modes
  420
- ADC Interrupts
  420
- Table 72. Low Power Modes
  420
- Table 73. ADC Interrupts in Single and Non-Buffered Continuous Mode (ADC1 and ADC2)
  420
- Table 74. ADC Interrupts in Buffered Continuous Mode (ADC1)
  421
- Table 75. ADC Interrupts in Scan Mode (ADC1)
  422
- Data Alignment
  423
- Reading the Conversion Result
  423
- Figure 163. Right Alignment of Data
  423
- Figure 164. Left Alignment of Data
  423
- Schmitt Trigger Disable Registers
  424
- ADC Registers
  425

ST STM8A Application Note (12 pages)

Brand: ST | Category: Microcontrollers | Size: 0 MB

ST Categories

Motherboard Computer Hardware Microcontrollers Control Unit Controller

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ST STM8A Manuals

ST STM8A Reference Manual (449 pages)

Table of Contents

Central Processing Unit (CPU)

Boot ROM

Memory and Register Map

Flash Program Memory and Data EEPROM

Single Wire Interface Module (SWIM) and Debug Module (DM)

Interrupt Controller (ITC)

Power Supply

Reset (RST)

Clock Control (CLK)

Power Management

General Purpose I/O Ports (GPIO)

Auto-Wakeup (AWU)

Beeper (BEEP)

Independent Watchdog (IWDG)

Window Watchdog (WWDG)

Timer Overview

16-Bit Advanced Control Timer (TIM1)

16-Bit General Purpose Timers (TIM2, TIM3, TIM5)

8-Bit Basic Timer (TIM4, TIM6)

Serial Peripheral Interface (SPI)

Inter-Integrated Circuit (I 2 C) Interface

Universal Asynchronous Receiver Transmitter (UART)

Controller Area Network (Becan)

Analog/Digital Converter (ADC)

ST STM8A Application Note (12 pages)

Table of Contents

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