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ST STM32H74xI/G Getting Started

ST STM32H74xI/G Getting Started

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Getting started with STM32H74xI/G and STM32H75xI/G
Introduction
This application note is intended for system designers who develop applications based on
STM32H750 Value line, STM32H742, STM32H743/753, STM32H745/755 and
STM32H747/757 lines, and who need an implementation overview of the following
hardware features:
•
Power supply
•
Package selection
•
Clock management
•
Reset control
•
Boot mode settings
•
Debug management.
This document describes the minimum hardware resources required to develop an
application based on STM32H74xI/G and STM32H75xI/G microcontrollers.
Reference documents
The following documents are available on www.st.com:
• STM32H742xI/G and STM32H743xI/G datasheet
• STM32H745xI/G datasheet
• STM32H747xI/G datasheet
• STM32H750xB datasheet
• STM32H753xI/G datasheet
• STM32H755xI/G datasheet
• STM32H757xI/G datasheet
•
Oscillator design guide for STM8S, STM8A and STM32 microcontrollers application note
(AN2867)
• STM32 microcontroller system memory boot mode application note (AN2606).
Generic part numbers
STM32H74xI/G,
STM32H75xI/G
May 2019
Table 1. Applicable products
Corresponding product lines
STM32H742, STM32H750 Value, STM32H743/753,
STM32H745/755, STM32H747/757
AN4938 Rev 4
AN4938
Application note
hardware development
1/46
www.st.com
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Summary of Contents for ST STM32H74xI/G

  • Page 1 Boot mode settings • Debug management. This document describes the minimum hardware resources required to develop an application based on STM32H74xI/G and STM32H75xI/G microcontrollers. Reference documents The following documents are available on www.st.com: • STM32H742xI/G and STM32H743xI/G datasheet • STM32H745xI/G datasheet •...

  • Page 2: Table Of Contents

    Contents AN4938 Contents General information ......... 7 Power supplies .
  • Page 3 Recommended PCB routing guidelines for STM32H74xI/G and STM32H75xI/G devices ..... 37 PCB stack-up ..........37 Crystal oscillator .
  • Page 4 Contents AN4938 9.4.3 Quadrature serial parallel interface (QUADSPI) ....41 9.4.4 Embedded trace macrocell (ETM) ......43 Conclusion .
  • Page 5 Boot modes............. 25 Table 3. STM32H74xI/G and STM32H75xI/G bootloader communication peripherals ..26 Table 4.
  • Page 6 STM32H74xI/G and STM32H75xI/G ........

  • Page 7: General Information

    -based devices. Power supplies Introduction STM32H74xI/G and STM32H75xI/G devices require a 1.71 to 3.6 V operating voltage supply (V ), which can be reduced down to 1.62 V by using an external power supervisor and connecting PDR_ON pin to V (refer to the datasheets for details).

  • Page 8: Usb Transceiver Independent Power Supply

    Power supplies AN4938 • When an OPAMP is used, V equals 2.0 V. DDA_MIN • When a reference voltage (VREFBUF_OUT) is provided by the device on V pin, REF+ depends on the required level for this voltage. DDA_MIN Note: Refer to the product datasheets for more details on V reference voltage range.

  • Page 9: Figure 1. Vdd33Usb Connected To Vdd Power Supply

    AN4938 Power supplies Figure 1. VDD33USB connected to V power supply Figure 2. VDD33USB VDD50USB connected to external power supply 1. V can be any power supply voltage among V and V DD33USB DD50USB DDDSI 2. If the SMPS is available, V and V must be wired together to follow the same voltage sequence.

  • Page 10: Battery Backup Domain

    Power supplies AN4938 2.1.3 Battery backup domain Backup domain description To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when is turned off, V pin can be connected to an optional 1.2-3.6 V standby voltage supplied by a battery.

  • Page 11: Smps Step-Down Converter

    AN4938 Power supplies 2.1.5 SMPS step-down converter To optimize power consumption, some devices embed a high power-efficient DC/DC non- linear switched-mode power supply voltage down-converter regulator. It can be enabled via the SDEN bit of the PWR_CR3 register. The SMPS can be used to deliver power either in internal or external supply mode. Internal supply mode (Direct mode): domain direct supply follows the device system operating modes (Run, Stop CORE...

  • Page 12: Power Supply Scheme

    Power supplies AN4938 Power supply scheme Power supplies • = 1.62 to 3.6 V: external power supply for I/Os, Flash memory and system analog blocks such as reset and PLL This power supply is provided externally through VDD pins. VDD pins must be connected to V with external decoupling capacitors: one single tantalum or ceramic capacitor (of 4.7 µF minimum capacitance) for the package and a 100 nF ceramic...
  • Page 13 AN4938 Power supplies Four additional power supplies and pins are used on devices that feature the SMPS: • = 1.62 to 3.6 V: SMPS step-down converter power supply DDSMPS must be kept at the same voltage level as V DDSMPS VDDSMPS pin must be connected to an external 4.7 μF capacitor with a 100 mΩ...

  • Page 14: Figure 3. Power Supply Overview

    Power supplies AN4938 Figure 3. Power supply overview 1. The SMPS is available only on STM32H7x5I/G and STM32H7x7I/G microcontrollers. 2. The internal DSI regulator and PHY are available only on STM32H7x7I/G microcontrollers. 14/46 AN4938 Rev 4...

  • Page 15: Reset And Power Supply Supervisor

    AN4938 Power supplies Reset and power supply supervisor 2.3.1 Power-on reset (POR)/power-down reset (PDR) The devices have an integrated POR/PDR circuitry that allows a proper operation starting from 1.71 V. The devices remain in reset mode when V is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.

  • Page 16: Analog Voltage Detector (Avd)

    Power supplies AN4938 Figure 5. PVD threshold 2.3.3 Analog voltage detector (AVD) The AVD can be used to monitor V power supply by comparing it to a threshold selected through the ALS[1:0] bits of the PWR power control register (PWR_CR1). The threshold value can be configured to 1.7, 2.1, 2.5 or 2.8 V (refer to the devices datasheets for the actual values).

  • Page 17: Internal Reset On

    AN4938 Power supplies Figure 6. Reset circuit 2.3.5 Internal reset ON On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled. For more details about the internal reset ON, refer to the datasheets. 2.3.6 Internal reset OFF This feature is available only on the packages featuring the PDR_ON pin.

  • Page 18: Figure 7. Power Supply Supervisor Interconnection With Internal Reset Off

    Power supplies AN4938 Figure 7. Power supply supervisor interconnection with internal reset OFF The supply ranges which never go below 1.71 V minimum should be better managed by the internal circuitry (no additional component needed, thanks to the fully embedded reset controller).

  • Page 19: Bypass Mode

    AN4938 Power supplies Figure 8. NRST circuitry timing example 2.3.7 Bypass mode The power management unit can be bypassed. This feature can be configured by software. When bypassed, the core power supply should be provided through VCAPx pins connected together. In Bypass mode, the internal voltage scaling is not managed internally, and the external voltage value must be consistent with the targeted maximum frequency (see datasheet for the actual VOS level).

  • Page 20: Alternate Function Mapping To Pins

    Alternate function mapping to pins AN4938 Alternate function mapping to pins In order to easily explore the peripheral alternate functions mapping to the pins it is recommended to use the STM32CubeMX tool available on http://www.st.com. Figure 9. STM32CubeMX example screen-shot 20/46 AN4938 Rev 4...

  • Page 21: Clocks

    AN4938 Clocks Clocks Four different clock sources can be used to drive the system clock (SYSCLK): • HSI oscillator clock • CSI oscillator clock. • HSE oscillator clock • Main PLL (PLL) clock The devices have the two following secondary clock sources: •...

  • Page 22: External User Clock (Hse Bypass)

    Clocks AN4938 4.1.1 External user clock (HSE bypass) In this mode, an external clock source must be provided. The user selects this mode by setting the HSEBYP and HSEON bits in the RCC clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC_IN pin.

  • Page 23: External Clock (Lse Bypass)

    AN4938 Clocks Figure 12. LSE external clock Figure 13. LSE crystal/ceramic resonators Figure 13: LSE crystal/ceramic resonators: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤...

  • Page 24: Clock Security System (Css)

    Clocks AN4938 Clock security system (CSS) The device provides two clock security systems (CSS), one for HSE oscillator and one for LSE oscillator. They can be independently enabled by software. When the clock security system on HSE is enabled, the clock detector is activated after the HSE oscillator startup delay, and disabled when this oscillator is stopped: •...

  • Page 25: Boot Configuration

    Boot configuration Boot configuration Boot mode selection In STM32H74xI/G and STM32H75xI/G microcontrollers, two different boot spaces can be selected through the BOOT pin and the boot base address programmed in the BOOT_ADD0 or BOOT_ADD1 option bytes as shown in the Table Table 2.

  • Page 26: Boot Pin Connection

    1. Resistor values are given only as a typical example. System bootloader mode The embedded bootloader code is located in the system memory. It is programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces.
  • Page 27 AN4938 Boot configuration Table 3. STM32H74xI/G and STM32H75xI/G bootloader communication peripherals Bootloader peripherals Bootloader pins SPI3 PC12/PC11/PC10/PA15 SPI4 PE11 / PE12 / PE13 / PE14 USB OTG_FS in Device mode PA11/PA12 (DFU) AN4938 Rev 4 27/46...

  • Page 28: Debug Management

    Figure 15. Host to board connection SWJ debug port (serial wire and JTAG) The core of STM32H74xI/G and STM32H75xI/G devices integrates the Serial Wire / JTAG ® Debug Port (SWJ-DP). It is an ARM standard CoreSight debug port that combines a 5-pin JTAG-DP interface and a 2-pin SW-DP interface.

  • Page 29: External Debug Trigger

    6.3.1 SWJ debug port pins Five pins are used as outputs from the STM32H74xI/G and STM32H75xI/G devices for the SWJ-DP as alternate functions of general-purpose I/Os. These pins are available on all packages.

  • Page 30: Flexible Swj-Dp Pin Assignment

    (note that the trace outputs are not assigned except if explicitly programmed by the debugger host). However, the STM32H74xI/G and STM32H75xI/G devices offer the possibility of disabling some or all of the SWJ-DP ports and so, of releasing the associated pins for general- purpose IO (GPIO) usage.

  • Page 31: Internal Pull-Up And Pull-Down On Jtag Pins

    JTAG I/O is released by the user software.” 6.3.4 SWJ debug port connection with standard JTAG connector Figure 16 shows the connection between STM32H74xI/G and STM32H75xI/G devices and a standard JTAG connector. Figure 16. JTAG connector implementation AN4938 Rev 4...

  • Page 32: Recommendations

    Recommendations AN4938 Recommendations Printed circuit board For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to the ground (V ) and another dedicated to the V supply. This provides a good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board.

  • Page 33: Other Signals

    AN4938 Recommendations Figure 17. Typical layout for V pair Other signals When designing an application, the EMC performance can be improved by closely studying: • Signals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals, and not the case for LED commands).

  • Page 34: Reference Design

    Reference design AN4938 Reference design Reference design description The reference design shown in Figure 18 is based on the STM32H753XI, a highly ® ® integrated microcontroller that combines the ARM Cortex -M7 32-bit RISC core running at up to 400 MHz with up to 2 Mbyte dual-bank Flash memory and 1 Mbytes of RAM (including 192 Kbytes of TCM RAM, 864 Kbytes of user RAM and 4 Kbytes of backup SRAM).

  • Page 35: Component References

    AN4938 Reference design Component references Table 8. Mandatory components Component name Reference Quantity Comments Microcontroller STM32H753XI TFBGA240 package Ceramic capacitors (decoupling Capacitor 100 nF capacitors) Ceramic capacitor (decoupling Capacitor 4.7 µF capacitor) Ceramic capacitor (regulator Capacitor 2.2 µF capacitor) Table 9. Optional components Components Reference Quantity...

  • Page 36: Figure 18. Stm32H753Xi Reference Schematic

    Figure 18. STM32H753XI reference schematic...

  • Page 37: Recommended Pcb Routing Guidelines For Stm32H74Xi/G And Stm32H75Xi/G Devices

    AN4938 Recommended PCB routing guidelines for STM32H74xI/G and STM32H75xI/G devices Recommended PCB routing guidelines for STM32H74xI/G and STM32H75xI/G devices PCB stack-up In order to reduce the reflections on high speed signals, it is necessary to match the impedance between the source, sink and transmission lines. The impedance of a signal trace depends on its geometry and its position with respect to any reference planes.

  • Page 38: Crystal Oscillator

    Figure 22 shows an example of decoupling capacitor placement underneath STM32H74xI/G and STM32H75xI/G devices, closer to the pins and with less vias. 38/46 AN4938 Rev 4...

  • Page 39: Figure 21. Decoupling Capacitor Placement Depending On Package Type

    AN4938 Recommended PCB routing guidelines for STM32H74xI/G and STM32H75xI/G devices Figure 21. Decoupling capacitor placement depending on package type Figure 22. Example of decoupling capacitor placed underneath the STM32H74xI/G and STM32H75xI/G AN4938 Rev 4 39/46...

  • Page 40: High Speed Signal Layout

    + N*C where the host is an Host Card STM32H74xI/G and STM32H75xI/G device, bus is all the signals and Card is SD card. 9.4.2 Flexible memory controller (FMC) interface Interface connectivity The FMC controller and in particular SDRAM memory controller which has many signals, most of them have a similar functionality and work together.

  • Page 41: Quadrature Serial Parallel Interface (Quadspi)

    AN4938 Recommended PCB routing guidelines for STM32H74xI/G and STM32H75xI/G devices Interface signal layout guidelines • Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR and GND Trace the impedance: 50 Ω ± 10% •...
  • Page 42 Recommended PCB routing guidelines for STM32H74xI/G and STM32H75xI/G devices AN4938 Interface signal layout guidelines • Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR and GND • Trace the impedance: 50 W ± 10% •...

  • Page 43: Embedded Trace Macrocell (Etm)

    AN4938 Recommended PCB routing guidelines for STM32H74xI/G and STM32H75xI/G devices • Avoid using a serpentine routing for the clock signal and as less via(s) as possible for the whole path. a via alters the impedance and adds a reflection to the signal.

  • Page 44: Conclusion

    Conclusion AN4938 Conclusion This application note should be used as a reference when starting a new design with an STM32H74xI/G and STM32H75xI/G microcontroller. 44/46 AN4938 Rev 4...

  • Page 45: Revision History

    AN4938 Revision history Revision history Table 10. Document revision history Date Revision Changes 13-Jun-2017 Initial release. Added Section 1: General information. 26-Jan-2018 Updated Figure 18: STM32H753XI reference schematic. Document generalized to all STM32H74xx and STM32H75xx. Added Table 1: Applicable products on cover page.
  • Page 46 ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

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