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ST STM8S Reference Manual

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Introduction
This reference manual provides complete information for application developers on how to
use STM8S and STM8A microcontroller memory and peripherals.
The STM8A is a family of microcontrollers designed for automotive applications, with
different memory densities, packages and peripherals:
■
The medium density STM8A devices are the STM8AF622x/4x, STM8AF6266/68,
STM8AF612x/4x, and STM8AF6166/68 microcontrollers with 8 to 32 Kbytes of Flash
memory.
■
The high density STM8A devices are the STM8AF52xx STM8AF6269/8x/Ax,
STM8AF51xx, and STM8AF6169/7x/8x/9x/Ax microcontrollers with 32 to 128 Kbytes of
Flash memory.
The STM8S is a family of microcontrollers designed for general purpose applications, with
different memory densities, packages and peripherals.
■
The value line low density STM8S devices are the STM8S003xx microcontrollers with
8 Kbytes of Flash memory.
■
The value line medium density STM8S devices are the STM8S005xx microcontrollers
with 32 Kbytes of Flash memory.
■
The value line high density STM8S devices are the STM8S007xx microcontrollers with
64 Kbytes of Flash memory.
■
The access line low density STM8S devices are the STM8S103xx and STM8S903xx
microcontrollers with 8 Kbytes of Flash memory.
■
The access line medium density STM8S devices are the STM8S105xx microcontrollers
with 16 to 32-Kbytes of Flash memory.
■
The performance line high density STM8S devices are the STM8S207xx and
STM8S208xx microcontrollers with 32 to 128 Kbytes of Flash memory.
Refer to the product datasheet for ordering information, pin description, mechanical and
electrical device characteristics, and for the complete list of available peripherals.
Reference documents
■
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S and STM8A Flash programming manual (PM0051), and to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
■
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
■
The bootloader user manual (UM0560) describes the usage of the integrated ROM
bootloader.
December 2011
STM8S and STM8A microcontroller families
Doc ID 14587 Rev 8
RM0016
Reference manual
www.st.com
1/449

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  • Page 1 Reference documents ■ For information on programming, erasing and protection of the internal Flash memory please refer to the STM8S and STM8A Flash programming manual (PM0051), and to the STM8 SWIM communication protocol and debug module user manual (UM0470). ■...

  • Page 2: Table Of Contents

    Memory organization ........36 4.4.1 STM8S and STM8A memory organization ..... . 36 4.4.2 Memory access/ wait state configuration .
  • Page 3 RM0016 Contents 4.5.3 Enabling write access to option bytes ......46 Memory programming ........46 4.6.1 Read-while-write (RWW) .
  • Page 4 Contents RM0016 Interrupt mapping ......... . . 66 ITC and EXTI registers .
  • Page 5 RM0016 Contents Clock-out capability (CCO) ........88 CLK interrupts .
  • Page 6 Contents RM0016 11.6 Low power modes ......... 108 11.7 Input mode details .
  • Page 7 RM0016 Contents 13.3.1 Beeper control/status register (BEEP_CSR) ....121 13.3.2 Beeper register map and reset values ......121 Independent watchdog (IWDG) .
  • Page 8 Contents RM0016 17.3.2 Write sequence for 16-bit TIM1_ARR register ....140 17.3.3 Prescaler ..........140 17.3.4 Up-counting mode .
  • Page 9 RM0016 Contents 17.7.12 Capture/compare mode register 4 (TIM1_CCMR4) ....200 17.7.13 Capture/compare enable register 1 (TIM1_CCER1) ....201 17.7.14 Capture/compare enable register 2 (TIM1_CCER2) .
  • Page 10 Contents RM0016 18.6.4 Interrupt enable register (TIMx_IER) ......226 18.6.5 Status register 1 (TIMx_SR1) ....... 227 18.6.6 Status register 2 (TIMx_SR2) .
  • Page 11 RM0016 Contents 19.6.9 Auto-reload register (TIMx_ARR) ......250 19.6.10 TIM4/TIM6 register map and reset values ..... . 251 Serial peripheral interface (SPI) .
  • Page 12 Contents RM0016 21.4.3 Error conditions ......... . 289 21.4.4 SDA/SCL line control .
  • Page 13 RM0016 Contents 22.4 LIN mode functional description ....... 333 22.4.1 Master mode .
  • Page 14 Contents RM0016 23.5.1 Silent mode ..........367 23.5.2 Loop back mode .
  • Page 15 RM0016 Contents 24.2 ADC main features ......... 411 24.3 ADC extended features .
  • Page 16 Contents RM0016 24.11.18 ADC watchdog control register low (ADC_AWCRL) ....436 24.12 ADC register map and reset values ......437 Revision history .
  • Page 17 RM0016 List of tables List of tables Table 1. Interrupt levels ............26 Table 2.
  • Page 18 List of tables RM0016 Table 49. C Interrupt requests ........... . 292 Table 50.
  • Page 19 Figure 9. UBC area size definition on low density STM8S devices ......41 Figure 10.
  • Page 20 List of figures RM0016 Figure 47. External trigger input block diagram ........152 Figure 48.
  • Page 21 RM0016 List of figures (BDM = 0 and RXONLY = 0). Case of continuous transfers..... . . 263 Figure 97. TXE/BSY in slave transmit-only mode (BDM = 0 and RXONLY = 0).
  • Page 22 List of figures RM0016 Figure 145. Transmit mailbox states ..........370 Figure 146.

  • Page 23: Central Processing Unit (Cpu)

    RM0016 Central processing unit (CPU) Central processing unit (CPU) Introduction The CPU has an 8-bit architecture. Six internal registers allow efficient data manipulations. The CPU is able to execute 80 basic instructions. It features 20 addressing modes and can address six internal registers. For the complete description of the instruction set, refer to the STM8 microcontroller family programming manual (PM0044).

  • Page 24: Figure 1. Programming Model

    (with the address given in the datasheets). For applications written in assembler, you can use either the startup function provided by ST or write your own by initializing the stack pointer with the correct address.

  • Page 25: Figure 2. Stacking Order

    RM0016 Central processing unit (CPU) Figure 2. Stacking order INTERRUPT GENERATION (execute pipeline) Complete instruction in execute stage (1-6 cycles latency) PUSH PCL PUSH PCH PUSH PCE PUSH Y PUSH X PUSH A 9 CPU CYCLES PUSH CC JUMP TO INTERRUPT ROUTINE GIVEN BY THE INTERRUPT VECTOR STACK (PUSH) UNSTACK...

  • Page 26: Table 1. Interrupt Levels

    Central processing unit (CPU) RM0016 Table 1. Interrupt levels Interruptability Priority Interruptable main Lowest Interruptable level 1 Interruptable level 2 Highest Non interruptable ● H: Half carry bit The H bit is set to 1 when a carry occurs between the bits 3 and 4 of the ALU during an ADD or ADC instruction.

  • Page 27: Stm8 Cpu Register Map

    RM0016 Central processing unit (CPU) Example: Addition $B5 + $94 = "C" + $49 = $149 1.2.2 STM8 CPU register map The CPU registers are mapped in the STM8 address space as shown inTable 2. These registers can only be accessed by the debug module but not by memory access instructions executed in the core.

  • Page 28: Swim Disable

    Central processing unit (CPU) RM0016 1.3.2 SWIM disable By default, after an MCU reset, the SWIM pin is configured to allow communication with an external tool for debugging or Flash/EEPROM programming. This pin can be configured by the application for use as a general purpose I/O. This is done by setting the SWD bit in the CFG_GCR register.

  • Page 29: Boot Rom

    RM0016 Boot ROM Boot ROM The internal 2 Kbyte boot ROM (available in some devices) contains the bootloader code. Its main tasks are to download the application program to the internal Flash/EEPROM through the SPI, CAN, or UART interface, and to program the code, data, option bytes and interrupt vectors in internal Flash/EEPROM.

  • Page 30: Memory And Register Map

    Memory and register map RM0016 Memory and register map For details on the memory map, I/O port hardware register map and CPU/SWIM/debug module/interrupt controller registers, refer to the product datasheets. Memory layout 3.1.1 Memory map Figure 3. Memory map 00 000h Stack RAM upper limit Reserved...

  • Page 31: Stack Handling

    RM0016 Memory and register map 3.1.2 Stack handling Default stack model The stack of the STM8S and STM8A microcontrollers is implemented in the user RAM area. The default stack model is shown in Figure Figure 4. Default stack model Start address...

  • Page 32: Figure 5. Customized Stack Model

    RM0016 Customized stack model STM8S and STM8A stack pointer handling allows a customized stack model to be implemented. This permits a flexible stack size without restrictions due to the stack roll-over limit. Implementing the customized stack also benefits portability of the software on products with different memory configurations.

  • Page 33: Register Description Abbreviations

    RM0016 Memory and register map Register description abbreviations In the register descriptions of each chapter in this reference manual, the following abbreviations are used: Table 4. List of abbreviations Abbreviation Description read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits.

  • Page 34: Flash Program Memory And Data Eeprom

    Flash program memory and data EEPROM RM0016 Flash program memory and data EEPROM Introduction The embedded Flash program memory and data EEPROM memories are controlled by a common set of registers. Using these registers, the application can program or erase memory contents and set write protection, or configure specific low power modes.

  • Page 35: Main Flash Memory Features

    RM0016 Flash program memory and data EEPROM Main Flash memory features ● STM8S and STM8A EEPROM is divided into two memory areas – Up to 128 Kbytes of Flash program memory. The density differs according to the device. Refer to Section 4.4: Memory organization...

  • Page 36: Memory Organization

    Flash program memory and data EEPROM RM0016 Memory organization 4.4.1 STM8S and STM8A memory organization STM8S and STM8A EEPROM is organized in 32-bit words (4 bytes per word). The memory organization differs according to the devices: ● Low density STM8S devices –...
  • Page 37 The EEPROM access time allows the device to run up to 16 MHz. For clock frequencies above 16 MHz, Flash/data EEPROM access must be configured for 1 wait state. This is enabled by the device option byte (refer to the option bytes section of the STM8S and STM8A datasheets).

  • Page 38: Figure 6. Flash Memory And Data Eeprom Organization On Low Density Stm8S

    Flash program memory and data EEPROM RM0016 Figure 6. Flash memory and data EEPROM organization on low density STM8S 1 page = 1 block = 64 bytes 0x00 4000 DATA MEMORY (up to 640 bytes) DATA EEPROM 0x00 427F 0x00 4800...

  • Page 39: Figure 7. Flash Memory And Data Eeprom Organization On Medium Density Stm8S And Stm8A

    RM0016 Flash program memory and data EEPROM Figure 7. Flash memory and data EEPROM organization on medium density STM8S and STM8A 1 page = 512 bytes 1 block = 128 bytes 00 4000h DATA MEMORY (up to 1 Kbyte) DATA EEPROM...

  • Page 40: Memory Access/ Wait State Configuration

    Flash program memory and data EEPROM RM0016 Figure 8. Flash memory and data EEPROM organization high density STM8S and STM8A 1 page = 512 bytes 1 block = 128 bytes 0x00 4000 DATA MEMORY (up to 2 Kbytes) DATA EEPROM...

  • Page 41: Figure 9. Ubc Area Size Definition On Low Density Stm8S Devices

    UBC area memory mapping and to the option byte section in the datasheets for more details on the UBC option byte. Figure 9. UBC area size definition on low density STM8S devices 0x00 8000 64 bytes Page 0...

  • Page 42: Figure 10. Ubc Area Size Definition On Medium Density Stm8S And Stm8A With Up To 32 Kbytes Of Flash Program Memory

    Flash program memory and data EEPROM RM0016 Figure 10. UBC area size definition on medium density STM8S and STM8A with up to 32 Kbytes of Flash program memory 0x00 8000 Interrupt vector table Page 0 0x00 807F 0x00 8200 512 bytes...

  • Page 43: Data Eeprom (Data)

    RM0016 Flash program memory and data EEPROM Figure 11. UBC area size definition on high density STM8S and STM8A with up to 128 Kbytes of Flash program memory 0x00 8000 Interrupt vector table Page 0 0x00 807F 0x00 8200 512 bytes...

  • Page 44: Memory Protection

    ICP mode (using the SWIM interface) is forbidden, whatever the write protection settings. Furthermore, on medium and high density STM8S and STM8A, the debug module (DM) cannot start code execution by the CPU when the readout protection is active, and the CPU is stalled.
  • Page 45 RM0016 Flash program memory and data EEPROM The following steps are required to disable write protection of the main program area: Write a first 8-bit key into the FLASH_PUKR register. When this register is written for the first time after a reset, the data bus content is not latched into the register, but compared to the first hardware key value (0x56).

  • Page 46: Enabling Write Access To Option Bytes

    Flash program memory and data EEPROM RM0016 4.5.3 Enabling write access to option bytes The procedure for enabling write access to the option byte area is the same as the one used for data EEPROM. However, the OPT bit in the Flash control register 2 (FLASH_CR2) must be set, and the corresponding NOPT bit in the...

  • Page 47: Word Programming

    RM0016 Flash program memory and data EEPROM Automatic fast byte programming The programming duration can vary according to the initial content of the target address. If the word (4 bytes) containing the byte to be programmed is not empty, the whole word is automatically erased before the program operation.
  • Page 48 Flash program memory and data EEPROM RM0016 Block operations can be performed both to the main program memory and DATA area: ● In the main program memory: Block program operations to the main program memory have to be executed totally from RAM.

  • Page 49: Option Byte Programming

    Nevertheless, part of the application must have been previously programmed in the Flash program memory using ICP. Refer to the STM8S and STM8A Flash programming manual (PM0051) and STM8 SWIM protocol and debug manual (UM0470) for more information on programming procedures.

  • Page 50: Table 6. Memory Access Versus Programming Method

    Flash program memory and data EEPROM RM0016 Table 6. Memory access versus programming method Access from Mode Memory Area core User boot code area (UBC) Readout Main program R/W/E protection Data EEPROM area (DATA) enabled Option bytes User, IAP, and bootloader (if available) User boot code area (UBC) Readout...

  • Page 51: Flash Registers

    RM0016 Flash program memory and data EEPROM Flash registers 4.8.1 Flash control register 1 (FLASH_CR1) Address offset: 0x00 Reset value: 0x00 HALT AHALT Reserved Bits 7:4 Reserved Bit 3 HALT: Power-down in Halt mode This bit is set and cleared by software. 0: Flash in power-down mode when MCU is in Halt mode 1: Flash in operating mode when MCU is in Halt mode Bit 2 AHALT: Power-down in Active-halt mode...

  • Page 52: Flash Control Register 2 (Flash_Cr2)

    Flash program memory and data EEPROM RM0016 4.8.2 Flash control register 2 (FLASH_CR2) Address offset: 0x01 Reset value: 0x00 WPRG ERASE FPRG Reserved Bit 7 OPT: Write option bytes This bit is set and cleared by software. 0: Write access to option bytes disabled 1: Write access to option bytes enabled Bit 6 WPRG: Word programming This bit is set by software and cleared by hardware when the operation is completed.

  • Page 53: Flash Complementary Control Register 2 (Flash_Ncr2)

    RM0016 Flash program memory and data EEPROM 4.8.3 Flash complementary control register 2 (FLASH_NCR2) Address offset: 0x02 Reset value: 0xFF NOPT NWPRG NERASE NFPRG NPRG Reserved Bit 7 NOPT: Write option bytes This bit is set and cleared by software. 0: Write access to option bytes enabled 1: Write access to option bytes disabled Bit 6 NWPRG: Word programming...

  • Page 54: Flash Protection Register (Flash_Fpr)

    Flash program memory and data EEPROM RM0016 4.8.4 Flash protection register (FLASH_FPR) Address offset: 0x03 Reset value: 0x00 WPB5 WPB4 WPB3 WPB2 WPB1 WPB0 Reserved Bits 7:6 Reserved. Bits 5:0 WPB[5:0]: User boot code area protection bits These bits show the size of the boot code area. They are loaded at startup with the content of the UBC option byte.

  • Page 55: Data Eeprom Unprotection Key Register (Flash_Dukr)

    RM0016 Flash program memory and data EEPROM 4.8.7 Data EEPROM unprotection key register (FLASH_DUKR) Address offset: 0x0A Reset value: 0x00 MASS_DATA KEYS Bits 7:0 DUK[7:0]: Data EEPROM write unlock keys This byte is written by software (all modes). It returns 0x00 when read. Refer to Enabling write access to the DATA area on page 45 for the description of main...

  • Page 56: Flash Register Map And Reset Values

    Flash program memory and data EEPROM RM0016 4.8.9 Flash register map and reset values For details on the Flash register boundary addresses, refer to the general hardware register map in the datasheets. Table 7. Flash register map and reset values Address Register name FLASH_CR1...

  • Page 57: Single Wire Interface Module (Swim) And Debug Module (Dm)

    RM0016 Single wire interface module (SWIM) and debug module (DM) Single wire interface module (SWIM) and debug module (DM) Introduction In-circuit debugging mode or in-circuit programming mode are managed through a single wire hardware interface featuring ultrafast memory programming. Coupled with an in-circuit debugging module, it also offers a non-intrusive emulation mode, making the in-circuit debugger extremely powerful, close in performance to a full-featured emulator.

  • Page 58: Interrupt Controller (Itc)

    Interrupt controller (ITC) RM0016 Interrupt controller (ITC) ITC introduction ● Management of hardware interrupts – External interrupt capability on most I/O pins with dedicated interrupt vector and edge sensitivity setting per port – Peripheral interrupt capability ● Management of software interrupt (TRAP) ●...

  • Page 59: Table 8. Software Priority Levels

    RM0016 Interrupt controller (ITC) Table 8. Software priority levels Software priority Level Level 0 (main) Level 1 Level 2 High Level 3 (= software priority disabled) Figure 13. Interrupt processing flowchart PENDING RESET TRAP INTERRUPT Interrupt has the same or a lower software priority than current one I1:0...

  • Page 60: Servicing Pending Interrupts

    Interrupt controller (ITC) RM0016 6.2.1 Servicing pending interrupts Several interrupts can be pending at the same time. The interrupt to be taken into account is determined by the following two-step process: The highest software priority interrupt is serviced. If several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first.
  • Page 61 RM0016 Interrupt controller (ITC) TRAP interrupt occurs. The corresponding vector is then loaded in the PC register and bits I1 and I0 of the CCR register are set to disable interrupts (level 3). ● TRAP (non-maskable software interrupt) This software interrupt source is serviced when the TRAP instruction is executed. It is serviced as a TLI according to the flowchart shown in Figure A TRAP interrupt does not allow the processor to exit from Halt mode.

  • Page 62: Interrupts And Low Power Modes

    Interrupt controller (ITC) RM0016 Maskable interrupt sources Maskable interrupt vector sources are serviced if the corresponding interrupt is enabled and if its own interrupt software priority in ITC_SPRx registers is higher than the one currently being serviced (I1 and I0 in CCR register). If one of these two conditions is not met, the interrupt is latched and remains pending.

  • Page 63: Concurrent And Nested Interrupt Management

    RM0016 Interrupt controller (ITC) moments in order to execute a specific task. Some of these recurring tasks are short enough to be treated directly in an ISR (interrupt service routine), rather than going back to the main program. To cover this case, you can set the AL bit before entering Low power mode (by executing WFI instruction), then the interrupt routine returns directly to Low power mode.

  • Page 64: Nested Interrupt Management Mode

    Interrupt controller (ITC) RM0016 6.5.2 Nested interrupt management mode In this mode, interrupts are allowed during interrupt routines. This mode is activated as soon as an interrupt priority level lower than level 3 is set. The hardware priority is given in the following order from the lowest to the highest priority, that is: MAIN, IT4, IT3, IT2, IT1, IT0, and TRAP.

  • Page 65: External Interrupts

    RM0016 Interrupt controller (ITC) Figure 16. Nested interrupt management SOFTWARE PRIORITY LEVEL TRAP MAIN MAIN 11 / 10 External interrupts Five interrupt vectors are dedicated to external Interrupt events: ● 5 lines on Port A: PA[6:2] ● 8 lines on Port B: PB[7:0] ●...

  • Page 66: Interrupt Mapping

    Interrupt controller (ITC) RM0016 Table 11. Dedicated interrupt instruction set (continued) Instruction New description Function/example JRNM Jump if I1:0<>11 I1:0<>11 ? POP CC Pop CCR from the stack Memory => CCR PUSH CC Push CC on the stack CC =>Memory Enable interrupt (level 0 set) Load 10 in I1:0 of CCR Disable interrupt (level 3 set)

  • Page 67: Itc And Exti Registers

    RM0016 Interrupt controller (ITC) ITC and EXTI registers 6.9.1 CPU condition code register interrupt bits (CCR) Address: refer to the general hardware register map table in the datasheet. Reset value: 0x28 – Bits 5, 3 I[1:0]: Software interrupt priority bits These two bits indicate the software priority of the current interrupt request.

  • Page 68: Software Priority Register X (Itc_Sprx)

    Interrupt controller (ITC) RM0016 6.9.2 Software priority register x (ITC_SPRx) Address offset: 0x00 to 0x07 Reset value: 0xFF ITC_SPR1 VECT3SPR[1:0] VECT2SPR[1:0] VECT1SPR[1:0] VECT0SPR[1:0] ITC_SPR2 VECT7SPR[1:0] VECT6SPR[1:0] VECT5SPR[1:0] VECT4SPR[1:0] ITC_SPR3 VECT11SPR[1:0] VECT10SPR[1:0] VECT9SPR[1:0] VECT8SPR[1:0] ITC_SPR4 VECT15SPR[1:0] VECT14SPR[1:0] VECT13SPR[1:0] VECT12SPR[1:0] ITC_SPR5 VECT19SPR[1:0] VECT18SPR[1:0] VECT17SPR[1:0] VECT16SPR[1:0]...

  • Page 69: External Interrupt Control Register 1 (Exti_Cr1)

    RM0016 Interrupt controller (ITC) 6.9.3 External interrupt control register 1 (EXTI_CR1) Address offset: 0x00 Reset value: 0x00 PDIS[1:0] PCIS[1:0] PBIS[1:0] PAIS[1:0] Bits 7:6 PDIS[1:0]: Port D external interrupt sensitivity bits These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They define the sensitivity of Port D external interrupts.

  • Page 70: External Interrupt Control Register 1 (Exti_Cr2)

    Interrupt controller (ITC) RM0016 6.9.4 External interrupt control register 1 (EXTI_CR2) Address offset: 0x01 Reset value: 0x00 TLIS PEIS[1:0] Reserved Bits 7:3 Reserved. Bit 2 TLIS: Top level interrupt sensitivity This bit is set and cleared by software. This bit can be written only when external interrupt is disabled on the corresponding GPIO port (PD7 or PC3, refer to Section 6.6: External interrupts on page...

  • Page 71: Itc And Exti Register Map And Reset Values

    RM0016 Interrupt controller (ITC) 6.9.5 ITC and EXTI register map and reset values Table 12. Interrupt register map Add. Register offset name ITC-SPR block ITC_SPR1 VECT3SPR1 VECT3SPR0 VECT2SPR1 VECT2SPR0 VECT1SPR1 VECT1SPR0 Reserved Reserved 0x00 Reset value ITC_SPR2 VECT7SPR1 VECT7SPR0 VECT6SPR1 VECT6SPR0 VECT5SPR1 VECT5SPR0...

  • Page 72: Power Supply

    Power supply RM0016 Power supply The MCU has four distinct power supplies: ● : Main power supply (3 V to 5.5 V) ● : I/O power supply (3 V to 5.5 V) DDIO SSIO ● : Power supply for the analog functions ●...

  • Page 73: Reset (Rst)

    RM0016 Reset (RST) Reset (RST) There are 9 reset sources: ● External reset through the NRST pin ● Power-on reset (POR) ● Brown-out Reset (BOR) ● Independent watchdog reset (IWDG) ● Window watchdog reset (WWDG) ● Software reset ● SWIM reset ●...

  • Page 74: Internal Reset Sources

    Reset (RST) RM0016 An internal temporization maintains a pulse of duration t whatever the internal reset OP(NRST) source. An additional internal weak pull-up ensures a high level on the reset pin when the reset is not forced. Internal reset sources Each internal reset source is linked to a specific flag bit in the Reset status register (RST_SR)

  • Page 75: Watchdog Reset

    RM0016 Reset (RST) 8.3.2 Watchdog reset Refer to Section 15: Window watchdog (WWDG) Section 14: Independent watchdog (IWDG) for details. 8.3.3 Software reset The application software can trigger reset by clearing bit T6 in the WWDG_CR register. Refer to Section 15: Window watchdog (WWDG).

  • Page 76: Rst Register Description

    Reset (RST) RM0016 RST register description 8.4.1 Reset status register (RST_SR) Address offset: 0x00 Reset value: 0xXX EMCF SWIMF ILLOPF IWDGF WWDGF Reserved rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 7:5 Reserved. Bit 4 EMCF: EMC reset flag This bit is set by hardware and cleared by software writing “1”. 0: No EMC reset occurred 1: An EMC reset occurred (possible cause: complementary register or option byte mismatch).

  • Page 77: Clock Control (Clk)

    RM0016 Clock control (CLK) Clock control (CLK) The clock controller is designed to be powerful, very robust, and at the same time easy to use. Its purpose is to allow you to obtain the best performance in your application while at the same time get the full benefit of all the microcontroller’s power saving capabilities.

  • Page 78: Figure 20. Clock Tree

    Clock control (CLK) RM0016 Figure 20. Clock tree CKM[7:0] HSE Ext. CPUDIV[2:0] fHSE OSCIN HSE OSC 1-24MHz OSCOUT EXTCLK OPT BIT fCPU fMASTER Master Clock Switch HSIDIV[1:0] /128 fHSI fHSIDIV HSI RC 16 MHz To CPU and window watchdog LSI_EN OPT BIT fLSI LSI RC 128 kHz...

  • Page 79: Master Clock Sources

    RM0016 Clock control (CLK) Master clock sources 4 different clock sources can be used to drive the master clock: ● 1-24 MHz high speed external crystal oscillator (HSE) ● Up to 24 MHz high speed user-external clock (HSE user-ext) ● 16 MHz high speed internal RC oscillator (HSI) ●...

  • Page 80: Hsi

    Clock control (CLK) RM0016 External crystal/ceramic resonator (HSE crystal) The 1 to 24 MHz external oscillator has the advantage of producing a very accurate rate on the main clock with 50% duty cycle. The associated hardware configuration is shown in Figure 21.

  • Page 81: Lsi

    HSI clock as master clock after MCU wakeup from Halt or Active-halt (see Low power chapter). Calibration Each device is factory calibrated by ST. After reset, the factory calibration value is automatically loaded in an internal calibration register. If the application is subject to voltage or temperature variations this may affect the RC oscillator speed.

  • Page 82: Master Clock Switching

    At startup, the clock is not released until this bit is set by hardware. Calibration Like the HSI RC, the LSI RC device is factory calibrated by ST. However, it is not possible to perform further trimming. Note:...
  • Page 83 RM0016 Clock control (CLK) The SWBSY bit is cleared and the new clock source replaces the old one. The SWIF flag in the CLK_SWCR is set and an interrupt is generated if the SWIEN bit is set. Manual switching The manual switching is not as immediate as the automatic switching but it offers to the user a precise control of the switch event time.

  • Page 84: Figure 22. Clock Switching Flowchart (Automatic Mode Example)

    Clock control (CLK) RM0016 Figure 22. Clock switching flowchart (automatic mode example) HARDWARE ACTION SOFTWARE ACTION Reset MCU in Run mode with HSI/8 Set SWEN bit in CLK_SWCR Set SWIEN bit in CLK_SWCR to enable interrupt if suitable Write target clock source in CLK_SWR Switch busy SWBSY Target clock source powered on...

  • Page 85: Low Speed Clock Selection

    RM0016 Clock control (CLK) Figure 23. Clock switching flowchart (manual mode example) HARDWARE ACTION SOFTWARE ACTION Reset MCU in Run mode with HSI/8 Set SWIEN bit in CLK_SWCR to enable interrupt if suitable Write target clock source in CLK_SWR Switch busy SWBSY Target clock source powered on Target clock source ready after...

  • Page 86: Peripheral Clock Gating (Pcg)

    Clock control (CLK) RM0016 Peripheral clock gating (PCG) Gating the clock to unused peripherals helps reduce power consumption. Peripheral clock Gating (PCG) mode allows you to selectively enable or disable the f clock MASTER connection to the following peripherals at any time in Run mode: ●...

  • Page 87: Clock Security System (Css)

    RM0016 Clock control (CLK) Clock security system (CSS) The Clock Security System (CSS) monitors HSE crystal clock source failures. When depends on HSE crystal, i.e. when HSE is selected, if the HSE clock fails due to a MASTER broken or disconnected resonator or any other reason, the clock controller activates a stall- safe recovery mechanism by automatically switching f to the auxiliary clock source MASTER...

  • Page 88: Clock-Out Capability (Cco)

    Clock control (CLK) RM0016 Clock-out capability (CCO) The configurable Clock Output (CCO) capability allows you to output a clock on the external CCO pin. You can select one of 6 clock signals as CCO clock: ● ● ● HSIDIV ● ●...

  • Page 89: Clk Register Description

    RM0016 Clock control (CLK) CLK register description 9.9.1 Internal clock register (CLK_ICKR) Address offset: 0x00 Reset value: 0x01 REGAH LSIRDY LSIEN HSIRDY HSIEN Reserved Bits 7:6 Reserved, must be kept cleared. Bit 5 REGAH: Regulator power off in Active-halt mode This bit is set and cleared by software.

  • Page 90: External Clock Register (Clk_Eckr)

    Clock control (CLK) RM0016 Bit 0 HSIEN: High speed internal RC oscillator enable This bit is set and cleared by software. It is set by hardware whenever the HSI oscillator is required, for example: – When activated as safe oscillator by the CSS –...

  • Page 91: Clock Master Status Register (Clk_Cmsr)

    RM0016 Clock control (CLK) 9.9.3 Clock master status register (CLK_CMSR) Address offset:0x03 Reset value: 0xE1 CKM[7:0] Bits 7:0 CKM[7:0]: Clock master status bits These bits are set and cleared by hardware. They indicate the currently selected master clock source. An invalid value occurring in this register will automatically generate an MCU reset. 0xE1: HSI selected as master clock source (reset value) 0xD2: LSI selected as master clock source (only if LSI_EN option bit is set) 0xB4: HSE selected as master clock source...

  • Page 92: Switch Control Register (Clk_Swcr)

    Clock control (CLK) RM0016 9.9.5 Switch control register (CLK_SWCR) Address offset: 0x05 Reset value: 0xXX SWIF SWIEN SWEN SWBSY Reserved rc_w0 Bits 7:4 Reserved. Bit 3 SWIF: Clock switch interrupt flag This bit is set by hardware and cleared by software writing 0. Its meaning depends on the status of the SWEN bit.

  • Page 93: Clock Divider Register (Clk_Ckdivr)

    RM0016 Clock control (CLK) 9.9.6 Clock divider register (CLK_CKDIVR) Address offset: 0x06 Reset value: 0x18 HSIDIV[1:0] CPUDIV[2:0] Reserved Bits 7:5 Reserved, must be kept cleared. Bits 4:3 HSIDIV[1:0]: High speed internal clock prescaler These bits are written by software to define the HSI prescaling factor. 00: f HSI RC output 01: f...

  • Page 94: Peripheral Clock Gating Register 1 (Clk_Pckenr1)

    Clock control (CLK) RM0016 9.9.7 Peripheral clock gating register 1 (CLK_PCKENR1) Address offset: 0x07 Reset value: 0xFF PCKEN1[7:0] Bits 7:0 PCKEN1[7:0]: Peripheral clock enable These bits are written by software to enable or disable the f clock to the corresponding MASTER peripheral (see Table...

  • Page 95: Peripheral Clock Gating Register 2 (Clk_Pckenr2)

    RM0016 Clock control (CLK) 9.9.8 Peripheral clock gating register 2 (CLK_PCKENR2) Address offset: 0x0A Reset value: 0xFF PCKEN2[7:0] Bits 7:0 PCKEN2[7:0]: Peripheral clock enable These bits are written by software to enable or disable the f clock to the corresponding MASTER peripheral.

  • Page 96: Clock Security System Register (Clk_Cssr)

    Clock control (CLK) RM0016 9.9.9 Clock security system register (CLK_CSSR) Address offset: 0x08 Reset value: 0x00 CSSD CSSDIE CSSEN Reserved rc_w0 Bits 7:4 Reserved, must be kept cleared. Bit 3 CSSD: Clock security system detection This bit is set by hardware and cleared by software writing 0. 0: CSS is off or no HSE crystal clock disturbance detected.

  • Page 97: Configurable Clock Output Register (Clk_Ccor)

    RM0016 Clock control (CLK) 9.9.10 Configurable clock output register (CLK_CCOR) Address offset: 0x09 Reset value: 0x00 CCOBSY CCORDY CCOSEL[3:0] CCOEN Reserved Bit 7 Reserved, must be kept cleared. Bit 6 CCOBSY: Configurable clock output busy This bit is set and cleared by hardware. It indicates that the selected CCO clock source is being switched-on and stabilized.

  • Page 98: Hsi Clock Calibration Trimming Register (Clk_Hsitrimr)

    These bits are written by software to fine tune the HSI calibration. Note: In high density STM8S and STM8A devices, only bits 2:0 are available. In other devices, bits 3:0 are available to achieve a better HSI resolution. Compatibility with bits 2:0 can be selected through options bytes (refer to datasheet).

  • Page 99: Swim Clock Control Register (Clk_Swimccr)

    RM0016 Clock control (CLK) 9.9.12 SWIM clock control register (CLK_SWIMCCR) Address offset: 0x0D Reset value: 0bXXXX XXX0 SWIMCLK Reserved Bits 7:1 Reserved. Bit 0 SWIMCLK SWIM clock divider This bit is set and cleared by software. 0: SWIM clock divided by 2 1: SWIM clock not divided by 2 Doc ID 14587 Rev 8 99/449...

  • Page 100: Clk Register Map And Reset Values

    Clock control (CLK) RM0016 9.10 CLK register map and reset values Table 19. CLK register map and reset values Address Register name offset CLK_ICKR LSIRDY LSIEN FHWU HSIRDY HSIEN REGAH 0x00 Reset value CLK_ECKR HSERDY HSEEN 0x01 Reset value 0x02 Reserved area (1 byte) CLK_CMSR CKM7...

  • Page 101: Power Management

    RM0016 Power management Power management By default, after a system or power reset, the microcontroller is in Run mode. In this mode the CPU is clocked by f and executes the program code, the system clocks are distributed to the active peripherals and the microcontroller is drawing full power. While in Run mode, still keeping the CPU running and executing code, the application has several ways to reduce power consumption, such as: ●...

  • Page 102: Clock Management For Low Consumption

    Power management RM0016 10.1.1 Clock management for low consumption Slowing down the system clock In Run mode, choosing the oscillator to be used as the system clock source is very important to ensure the best compromise between performance and consumption. The selection is done by programming the clock controller registers.

  • Page 103: Wait Mode

    RM0016 Power management 10.2.1 Wait mode Wait mode is entered from Run mode by executing a WFI (wait for interrupt) instruction: this stops the CPU but allows the other peripherals and interrupt controller to continue to run. Therefore the consumption decreases accordingly. Wait mode can be combined with PCG (peripheral clock gating), reduced CPU clock frequency and low mode clock source selection (LSI, HSI) to further reduce the power consumption of the device.

  • Page 104: Additional Analog Power Controls

    Power management RM0016 Main voltage regulator (MVR) auto power-off By default the main voltage regulator is kept on Active-halt mode. Keeping it active ensures fast wakeup from Active-halt mode. However, the current consumption of the MVR is non- negligible. To further reduce current consumption, the MVR regulator can be powered off automatically when the MCU enters Active-halt mode.

  • Page 105: General Purpose I/O Ports (Gpio)

    RM0016 General purpose I/O ports (GPIO) General purpose I/O ports (GPIO) 11.1 Introduction General purpose input/output ports are used for data transfers between the chip and the external world. An I/O port can contain up to eight pins. Each pin can be individually programmed as a digital input or digital output.

  • Page 106: Port Configuration And Usage

    General purpose I/O ports (GPIO) RM0016 Figure 24. GPIO block diagram P-BUFFER ALTERNATE (see table below) OUTPUT ALTERNATE ENABLE PULL-UP (see table below) OUTPUT ODR REGISTER PULL-UP DDR REGISTER CONDITION CR1 REGISTER SLOPE CONTROL PROTECTION CR2 REGISTER N-BUFFER DIODES (see table below) ADC_TDR REGISTER INPUT IDR REGISTER...

  • Page 107: Input Modes

    RM0016 General purpose I/O ports (GPIO) Table 21. I/O port configuration summary Diodes Mode Function Pull-up P-buffer to V to V Floating without interrupt Pull-up without Input interrupt Floating with interrupt Pull-up with interrupt Open drain output Push-pull output Open drain output, fast mode Output Push-pull, fast mode...

  • Page 108: Reset Configuration

    General purpose I/O ports (GPIO) RM0016 11.4 Reset configuration All I/O pins are generally input floating under reset (i.e. during the reset phase) and at reset state (i.e. after reset release). However, a few pins may have a different behavior. Refer to the datasheet pinout description for all details.

  • Page 109: Interrupt Capability

    RM0016 General purpose I/O ports (GPIO) 11.7.2 Interrupt capability Each I/O can be configured as an input with interrupt capability by setting the CR2x bit while the I/O is in input mode. In this configuration, a signal edge or level input on the I/O generates an interrupt request.

  • Page 110: Slope Control

    General purpose I/O ports (GPIO) RM0016 An alternate function output can be push-pull or pseudo-open drain depending on the peripheral and Control register 1 (Px_CR1) and slope can be controlled depending on the Control register 2 (Px_CR2) values. Examples: SPI output pins must be set-up as push-pull, fast slope for optimal operation. 11.8.2 Slope control The maximum frequency that can be applied to an I/O can be controlled by software using...

  • Page 111: Gpio Registers

    RM0016 General purpose I/O ports (GPIO) 11.9 GPIO registers The bit of each port register drives the corresponding pin of the port. 11.9.1 Port x output data register (Px_ODR) Address offset: 0x00 Reset value: 0x00 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0...

  • Page 112: Port X Data Direction Register (Px_Ddr)

    General purpose I/O ports (GPIO) RM0016 11.9.3 Port x data direction register (Px_DDR) Address offset: 0x02 Reset value: 0x00 DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0 Bits 7:0 DDR[7:0]: Data direction bits These bits are set and cleared by software to select input or output mode for a particular pin of a port.

  • Page 113: Port X Control Register 2 (Px_Cr2)

    RM0016 General purpose I/O ports (GPIO) 11.9.5 Port x control register 2 (Px_CR2) Address offset: 0x04 Reset value: 0x00 Bits 7:0 C2[7:0]: Control bits These bits are set and cleared by software. They select different functions in input mode and output mode.

  • Page 114: Auto-Wakeup (Awu)

    Auto-wakeup (AWU) RM0016 Auto-wakeup (AWU) 12.1 Introduction The AWU is used to provide an internal wakeup time base that is used when the MCU goes into Active-halt power saving mode. This time base is clocked by the low speed internal (LSI) RC oscillator clock or the HSE crystal oscillator clock divided by a prescaler.

  • Page 115: Awu Functional Description

    RM0016 Auto-wakeup (AWU) 12.3 AWU functional description 12.3.1 AWU operation To use the AWU, perform the following steps in order: Measure the LS clock frequency using the MSR bit in AWU_CSR register and TIM3 or TIM1 input capture 1. Define the appropriate prescaler value by writing to the APR [5:0] bits in the Asynchronous prescaler register (AWU_APR).

  • Page 116: Time Base Selection

    Auto-wakeup (AWU) RM0016 12.3.2 Time base selection Please refer to the Asynchronous prescaler register (AWU_APR) Timebase selection register (AWU_TBR) descriptions. The AWU time intervals depend on the values of: ● AWUTB[3:0] bits. This gives the counter output rank. ● APR[5:0] bits. This gives the prescaler division factor (APR 15 non-overlapped ranges of time intervals can be defined as follows: Table 25.

  • Page 117: Lsi Clock Frequency Measurement

    RM0016 Auto-wakeup (AWU) Example 1 ● = 128 kHz ● Target time interval = 6 ms The appropriate interval range is: 4 ms - 8 ms so the AWUTB[3:0] value is 0x5. The APR value is: 6 ms = 2 x APR =>...

  • Page 118: Awu Registers

    Auto-wakeup (AWU) RM0016 12.4 AWU registers 12.4.1 Control/status register (AWU_CSR) Address offset: 0x00 Reset value: 0x00 AWUF AWUEN Reserved Reserved rc_r Bits 7:6 Reserved Bit 5 AWUF: Auto-wakeup flag This bit is set by hardware when the AWU module generates an interrupt and cleared by reading the AWU_CSR register.

  • Page 119: Timebase Selection Register (Awu_Tbr)

    RM0016 Auto-wakeup (AWU) 12.4.3 Timebase selection register (AWU_TBR) Address offset: 0x02 Reset value: 0x00 AWUTB[3:0] Reserved Bits 7:4 Reserved Bits 3:0 AWUTB[3:0]: Auto-wakeup timebase selection These bits are written by software to define the time interval between AWU interrupts. AWU interrupts are enabled when AWUEN = 1.

  • Page 120: Beeper (Beep)

    Beeper (BEEP) RM0016 Beeper (BEEP) 13.1 Introduction This function generates a beep signal in the range of 1, 2 or 4 kHz when the LS clock is operating at a frequency of 128 kHz. Figure 26. Beep block diagram HSE clock (4- 24 MHz) CKAWUSEL PRSC[1:0] OPTION bit...

  • Page 121: Beeper Calibration

    RM0016 Beeper (BEEP) 13.2.2 Beeper calibration This procedure can be used to calibrate the LS 128 kHz clock in order to reach the standard frequency output, 1 kHz, 2 kHz or 4 kHz. Use the following procedure: Measure the LSI clock frequency (refer to Section 12.3.3: LSI clock frequency measurement above).

  • Page 122: Independent Watchdog (Iwdg)

    Independent watchdog (IWDG) RM0016 Independent watchdog (IWDG) 14.1 Introduction The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even if the main clock fails. 14.2 IWDG functional description Figure 27...

  • Page 123: Table 28. Watchdog Timeout Period (Lsi Clock Frequency = 128 Khz)

    RM0016 Independent watchdog (IWDG) Timeout period The timeout period can be configured through the IWDG_PR and IWDG_RLR registers. It is determined by the following equation: × × × where: T = Timeout period = 1/f (PR[2:0] + 2) P = 2 R = RLR[7:0]+1 The IWDG counter must be refreshed by software before this timeout period expires.

  • Page 124: Iwdg Registers

    Independent watchdog (IWDG) RM0016 14.3 IWDG registers 14.3.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0xXX KEY[7:0] Bits 7:0 KEY[7:0]: Key value The KEY_REFRESH value must be written by software at regular intervals, otherwise the watchdog generates an MCU reset when the counter reaches 0. If the IWDG is not enabled by option byte (see datasheet for option byte description), the KEY_ENABLE value is the first value to be written in this register.

  • Page 125: Reload Register (Iwdg_Rlr)

    RM0016 Independent watchdog (IWDG) 14.3.3 Reload register (IWDG_RLR) Address offset: 0x02 Reset value: 0xFF RL[7:0] RL[7:0]: Watchdog counter reload value These bits are write access protected (see Section 14.2). They are written by software to define the Bits 7:0 value to be loaded in the watchdog counter each time the value 0xAA is written in the IWDG_KR register.

  • Page 126: Window Watchdog (Wwdg)

    Window watchdog (WWDG) RM0016 Window watchdog (WWDG) 15.1 Introduction The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared.

  • Page 127: Figure 28. Watchdog Block Diagram

    RM0016 Window watchdog (WWDG) Figure 28. Watchdog block diagram WATCHDOG WINDOW REGISTER (WWDG_WR) RESET comparator = 1 when T6:0 > W6:0 Write WWDG_CR WATCHDOG CONTROL REGISTER (wWDG_CR) WDGA 6-BIT DOWNCOUNTER (CNT) WDG PRESCALER (from clock) DIV 12288 The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset.

  • Page 128: How To Program The Watchdog Timeout

    Window watchdog (WWDG) RM0016 15.4 How to program the watchdog timeout The formula below can be used to calculate the WWDG timeout, t , expressed in ms: WWDG × × 12288 T 5:0 WWDG where T is the peripheral clock period expressed in ms Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset.

  • Page 129: Wwdg Low Power Modes

    RM0016 Window watchdog (WWDG) Figure 30. Window watchdog timing diagram T[5:0] CNT downcounter WDGWR 0x7F time Refresh not allowed Refresh Window (step = 12288/f clk_wwdg_ck T6 bit Reset Table 30. Window watchdog timing example (MHz) T[6:0] 6.144 0.768 393.216 49.152 15.5 WWDG low power modes Table 31.

  • Page 130: Hardware Watchdog Option

    Window watchdog (WWDG) RM0016 15.6 Hardware watchdog option If hardware watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the WWDG_CR register is not used. Refer to the option byte description in the datasheet.

  • Page 131: Window Watchdog Register Map And Reset Values

    RM0016 Window watchdog (WWDG) Bits 6:0 W[6:0]: 7-bit window value These bits contain the window value to be compared to the downcounter. 15.10 Window watchdog register map and reset values Table 32. WWDG register map and reset values Address Register offset name WWDG_CR...

  • Page 132: Timer Overview

    RM0016 Timer overview The devices in the STM8S and STM8A family may be equipped with up to three different timer types: Advanced control (TIM1), general purpose (TIM2/TIM3/TIM5), and basic timers (TIM4/TIM6). The timers share the same architecture, but some have additional unique features.

  • Page 133: Timer Feature Comparison

    RM0016 Timer overview 16.1 Timer feature comparison Table 34. Timer feature comparison Capture/ Timer Counter Comple- Repet- External External Counter Prescaler compare synchro- Timer resol- mentary ition trigger break type factor chan- nization/ ution outputs counter input input nels chaining TIM1 Any integer With...

  • Page 134: Table 35. Glossary Of Internal Timer Signals

    Timer overview RM0016 Table 35. Glossary of internal timer signals (continued) Internal signal name Description Related figures External trigger from TIMx_ETR pin Figure 47: External trigger input block ETRF External trigger filtered diagram on page 152 External trigger ETRP prescaled Timer peripheral clock from clock controller MASTER...

  • Page 135: Table 36. Explanation Of Indices'i', 'N', And 'X

    RM0016 Timer overview Table 36. Explanation of indices‘i’, ‘n’, and ‘x’ Timer number: May be 1, 2, 3, 4, 5, 6 depending on the device Don’t care (for bits) 1. These indices are used in Section Section 18, and Section Doc ID 14587 Rev 8 135/449...

  • Page 136: 16-Bit Advanced Control Timer (Tim1)

    16-bit advanced control timer (TIM1) RM0016 16-bit advanced control timer (TIM1) This section gives a description of the full set of timer features. 17.1 Introduction TIM1 consists of a 16-bit up-down auto-reload counter driven by a programmable prescaler. The timer may be used for a variety of purposes, including: ●...

  • Page 137: Tim1 Main Features

    RM0016 16-bit advanced control timer (TIM1) 17.2 TIM1 main features TIM1 features include: ● 16-bit up, down, up/down counter auto-reload counter ● Repetition counter to update the timer registers only after a given number of cycles of the counter. ● 16-bit programmable prescaler allowing the counter clock frequency to be divided “on the fly”...

  • Page 138: Figure 31. Tim1 General Block Diagram

    16-bit advanced control timer (TIM1) RM0016 Figure 31. TIM1 general block diagram MASTER/DIV TRGO to TIM5/TIM6 or to ADC TIM1_ETR CLOCK/TRIGGER CONTROLLER TRGO from other TIM timers Clock/reset/enable TIME BASE UNIT Repetition counter CK_CNT CK_PSC Prescaler UP-DOWN COUNTER Auto-reload register CAPTURE COMPARE ARRAY CC1I TIM1_CH1...

  • Page 139: Tim1 Time Base Unit

    RM0016 16-bit advanced control timer (TIM1) 17.3 TIM1 time base unit The timer has a time base unit that includes: ● 16-bit up/down counter ● 16-bit auto-reload register ● Repetition counter ● Prescaler Figure 32. Time base unit TIM1_ARRH, ARRL TIM1_RCR Auto-reload register Repetition counter register...

  • Page 140: Reading And Writing To The 16-Bit Counter

    16-bit advanced control timer (TIM1) RM0016 17.3.1 Reading and writing to the 16-bit counter There is no buffering when writing to the counter. Both TIM1_CNTRH and TIM1_CNTRL can be written at any time, so it is suggested not to write a new value into the counter while it is running to avoid loading an incorrect intermediate content.

  • Page 141: Up-Counting Mode

    RM0016 16-bit advanced control timer (TIM1) Read operations to the TIM1_PSCR registers access the preload registers, so no special care needs to be taken to read them. 17.3.4 Up-counting mode In up-counting mode, the counter counts from 0 to a user-defined compare value (content of the TIM1_ARR register).

  • Page 142: Figure 35. Counter Update When Arpe = 0 (Arr Not Preloaded) With Prescaler = 2

    16-bit advanced control timer (TIM1) RM0016 Figure 35. Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2 CK_PSC CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 32 33 34 35 36 01 02 03 04 05 06 07 COUNTER OVERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF)

  • Page 143: Down-Counting Mode

    RM0016 16-bit advanced control timer (TIM1) 17.3.5 Down-counting mode In down-counting mode, the counter counts from the auto-reload value (content of the TIM1_ARR register) down to 0. It then restarts from the auto-reload value and generates a counter underflow and a UEV, if the UDIS bit is 0 in the TIM1_CR1 register. Figure 37 shows an example of this counting mode.

  • Page 144: Figure 38. Counter Update When Arpe = 0 (Arr Not Preloaded) With Prescaler = 2

    16-bit advanced control timer (TIM1) RM0016 Figure 38. Counter update when ARPE = 0 (ARR not preloaded) with prescaler = 2 CK_PSC CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 05 04 03 02 01 35 34 33 32 31 30 2F COUNTER UNDERFLOW UPDATE EVENT (UEV) UPDATE INTERRUPT FLAG (UIF)

  • Page 145: Center-Aligned Mode (Up/Down Counting)

    RM0016 16-bit advanced control timer (TIM1) 17.3.6 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value of -1 (content of the TIM1_ARR register). This generates a counter overflow event. The counter then counts down to 0 and generates a counter underflow event.

  • Page 146: Figure 41. Counter Timing Diagram, F Ck_Cnt = F Ck_Psc , Tim1_Arr = 06H, Arpe = 1

    16-bit advanced control timer (TIM1) RM0016 Figure 41. Counter timing diagram, f , TIM1_ARR = 06h, ARPE = 1 CK_CNT CK_PSC CK_PSC CNT_EN TIMER CLOCK = CK_CNT COUNTER REGISTER 03 02 01 00 01 03 04 05 06 05 04 03 COUNTER UNDERFLOW COUNTER OVERFLOW UPDATE EVENT (UEV)

  • Page 147: Repetition Down-Counter

    RM0016 16-bit advanced control timer (TIM1) 17.3.7 Repetition down-counter Section 17.3: TIM1 time base unit describes how the UEV is generated with respect to counter overflows/underflows. It is generated only when the repetition down-counter reaches zero. This can be useful while generating PWM signals. This means that data are transferred from the preload registers to the shadow registers (TIM1_ARR auto-reload register, TIM1_PSCR prescaler register, and TIM1_CCRx capture/compare registers in compare mode) every ‘n’...

  • Page 148: Figure 42. Update Rate Examples Depending On Mode And Tim1_Rcr Register Settings

    16-bit advanced control timer (TIM1) RM0016 Figure 42. Update rate examples depending on mode and TIM1_RCR register settings Center-aligned mode Edge-aligned mode Up-counting Down-counting Counter TIM1_CNT TIM1_RCR = 0 TIM1_RCR = 1 TIM1_RCR = 2 TIM1_RCR = 3 TIM1_RCR re-synchronization (by SW) (by SW) (by SW)

  • Page 149: Tim1 Clock/Trigger Controller

    RM0016 16-bit advanced control timer (TIM1) 17.4 TIM1 clock/trigger controller The clock/trigger controller allows the timer clock sources, input triggers, and output triggers to be configured. The block diagram is shown in Figure 43. Figure 43. Clock/trigger controller block diagram MASTER ETRF Trigger...

  • Page 150: Internal Clock Source (Fmaster)

    16-bit advanced control timer (TIM1) RM0016 17.4.2 Internal clock source (f MASTER If both the clock/trigger mode controller and the external trigger input are disabled (SMS = 000 in TIM1_SMCR and ECE = 0 in the TIM1_ETR register), the CEN, DIR, and UG bits behave as control bits and can be changed only by software (except UG which remains cleared automatically).

  • Page 151: Figure 46. Control Circuit In External Clock Mode 1

    RM0016 16-bit advanced control timer (TIM1) Procedure Use the following procedure to configure the up-counter and, for example, to count in response to a rising edge on the TI2 input: Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = 01 in the TIM1_CCMR2 register.

  • Page 152: External Clock Source Mode 2

    16-bit advanced control timer (TIM1) RM0016 17.4.4 External clock source mode 2 The counter can count at each rising or falling edge on the ETR. This mode is selected by writing ECE = 1 in the TIM1_ETR register. Figure 47 gives an overview of the external trigger input block.

  • Page 153: Trigger Synchronization

    RM0016 16-bit advanced control timer (TIM1) 17.4.5 Trigger synchronization There are four trigger inputs (refer to Table 35: Glossary of internal timer signals on page 133): ● ● ● ● TRGO from TIM5/TIM6 The TIM1 timer can be synchronized with an external trigger in three modes: Trigger standard mode, trigger reset mode and trigger gated mode.

  • Page 154: Figure 50. Control Circuit In Trigger Reset Mode

    16-bit advanced control timer (TIM1) RM0016 Trigger reset mode The counter and its prescaler can be re-initialized in response to an event on a trigger input. Moreover, if the URS bit from the TIM1_CR1 register is low, a UEV is generated. Then all the preloaded registers (TIM1_ARR, TIM1_CCRi) are updated.

  • Page 155: Figure 51. Control Circuit In Trigger Gated Mode

    RM0016 16-bit advanced control timer (TIM1) Trigger gated mode The counter can be enabled depending on the level of a selected input. Example Use the following procedure to enable the up-counter when TI1 input is low: Configure channel 1 to detect low levels on TI1. Configure the input filter duration (IC1F = 0000).

  • Page 156: Figure 52. Control Circuit In External Clock Mode 2 + Trigger Mode

    16-bit advanced control timer (TIM1) RM0016 Combining trigger modes with external clock mode 2 External clock mode 2 can be used with another trigger mode. For example, the ETR can be used as the external clock input, and a different input can be selected as trigger input (in trigger standard mode, trigger reset mode, or trigger gated mode).

  • Page 157: Synchronization Between Tim1, Tim5 And Tim6 Timers

    RM0016 16-bit advanced control timer (TIM1) 17.4.6 Synchronization between TIM1, TIM5 and TIM6 timers On some products, the timers are linked together internally for timer synchronization or chaining. When one timer is configured in master mode, it can output a trigger (TRGO) to reset, start, stop, or clock the counter of any other timer configured in slave mode.

  • Page 158: Figure 54. Trigger/Master Mode Selection Blocks

    16-bit advanced control timer (TIM1) RM0016 Figure 54 presents an overview of the trigger selection and the master mode selection blocks. Figure 54. Trigger/master mode selection blocks TRIGGER SELECTION BLOCK TIMx_SMCR TS[2:0] MASTER MODE SELECTION BLOCK ITR0 CNT_EN TRGO from TIM6 MATCH1 TRGO ITR2...

  • Page 159: Figure 56. Gating Timer B With Oc1Ref Of Timer A

    RM0016 16-bit advanced control timer (TIM1) Using one timer to enable another timer Example 1 The enable of timer B is controlled with the output compare 1 of timer A (refer to Figure 56 for connections). Timer B counts on the divided internal clock only when OC1REF of timer A is high.

  • Page 160: Figure 57. Gating Timer B With The Counter Enable Signal Of Timer A (Cnt_En)

    16-bit advanced control timer (TIM1) RM0016 Example 2 Timer A and timer B are synchronized. Timer A is the master and starts from 0. Timer B is the slave and starts from E7h. The prescaler ratio is the same for both timers. Timer B stops when timer A is disabled by writing 0 to the CEN bit in the TIMx_CR1 register: Configure timer A master mode to send its output compare 1 reference (OC1REF) signal as trigger output (MMS = 100 in the TIMx_CR2 register).

  • Page 161: Figure 58. Triggering Timer B With The Uev Of Timer A (Timera-Uev)

    RM0016 16-bit advanced control timer (TIM1) Using one timer to start another timer Example 1 The enable of timer B is set with the UEV of timer A (refer to Figure 55 for connections). Timer B starts counting from its current value (which can be non-zero) on the divided internal clock as soon as the UEV is generated by timer A.

  • Page 162: Figure 59. Triggering Timer B With Counter Enable Cnt_En Of Timer A

    16-bit advanced control timer (TIM1) RM0016 Example 2 As in the previous example, both counters can be initialized before starting to count. Figure 59 shows the behavior, with the same configuration as in Figure 57, but, in trigger standard mode instead of trigger gated mode (SMS = 110 in the TIM1_SMCR register). Figure 59.

  • Page 163: Tim1 Capture/Compare Channels

    RM0016 16-bit advanced control timer (TIM1) Figure 60. Triggering Timer A and B with Timer A TI1 input MASTER Timer A-TI1 Timer A-CEN = CNT_EN Timer A-CK_PSC Timer A-CNT 02 03 04 05 06 07 08 09 Timer A-TIF Timer B-CEN = CNT_EN Timer B-CK_PSC Timer B-CNT 02 03 04 05 06 07 08 09...

  • Page 164: Write Sequence For 16-Bit Tim1_Ccri Registers

    16-bit advanced control timer (TIM1) RM0016 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are made in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter.

  • Page 165: Input Stage

    RM0016 16-bit advanced control timer (TIM1) 17.5.2 Input stage Figure 63. Channel input stage block diagram TI1F_ED to clock/trigger controller TI1FP1 Input Filter & TI1FP2 TIM1_CH1 EdgeDetector TI2FP1 Input Filter & TIM1_CH2 TI2FP2 EdgeDetector to capture/compare channels TI3FP3 Input Filter & TI3FP4 TIM1_CH3 EdgeDetector...

  • Page 166: Input Capture Mode

    16-bit advanced control timer (TIM1) RM0016 17.5.3 Input capture mode In input capture mode, the capture/compare registers (TIM1_CCRi) are used to latch the value of the counter after a transition detected on the corresponding ICi signal. When a capture occurs, the corresponding CCiIF flag (TIM1_SR1 register) is set. An interrupt can be sent if it is enabled, by setting the CCiIE bits in the TIM1_IER register.

  • Page 167: Figure 65. Pwm Input Signal Measurement

    RM0016 16-bit advanced control timer (TIM1) PWM input signal measurement This mode is a particular case of input capture mode (see Figure 65). The procedure is the same except: ● Two ICi signals are mapped on the same TIi input ●...

  • Page 168: Output Stage

    16-bit advanced control timer (TIM1) RM0016 Figure 66. PWM input signal measurement example 0004 0000 0001 0002 0003 0004 0000 TIM1_CNT TIM1_CCR1 0004 TIM1_CCR2 0002 IC2 Capture IC1 Capture pulse width measurement period measurement reset counter 17.5.4 Output stage The output stage generates an intermediate waveform called OCiREF (active high) which is then used for reference.

  • Page 169: Forced Output Mode

    RM0016 16-bit advanced control timer (TIM1) Figure 68. Detailed output stage of channel with complementary output (channel 1) TIM1_CH1 Output Enable ‘0’ Circuit OC1_DT CC1P Counter > CCR1 Output Mode OC1REF Deadtime TIM1_CCER1 Counter = CCR1 Controller Generator OC1N_DT TIM1_CH1N Output ‘0’...

  • Page 170: Figure 69. Output Compare Mode, Toggle On Oc1

    16-bit advanced control timer (TIM1) RM0016 The output compare mode is defined by the OCiM bits in the TIM1_CCMRi registers. The active or inactive level polarity is defined by the CCiP bits in the TIM1_CCERi registers. The TIM1_CCRi registers can be programmed with or without preload registers using the OCiPE bits in the TIM1_CCMRi registers.

  • Page 171: Pwm Mode

    RM0016 16-bit advanced control timer (TIM1) 17.5.7 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIM1_ARR register and a duty cycle determined by the value of the TIM1_CCRi registers.

  • Page 172: Figure 70. Edge-Aligned Counting Mode Pwm Mode 1 Waveforms (Arr = 8)

    16-bit advanced control timer (TIM1) RM0016 Figure 70. Edge-aligned counting mode PWM mode 1 waveforms (ARR = 8) COUNTER REGISTER OCiREF CCRx = 4 CCiIF OCiREF CCRx = 8 CCiIF OCiREF ‘1’ CCRx > 8 CCiIF ‘0’ OCiREF CCRx = 0 CCiIF Down-counting configuration Down-counting is active when the DIR bit in the TIM1_CR1 register is high.

  • Page 173: Figure 71. Center-Aligned Pwm Waveforms (Arr = 8)

    RM0016 16-bit advanced control timer (TIM1) Figure 71. Center-aligned PWM waveforms (ARR = 8) COUNTER REGISTER OCiREF CMS=01 CCRx=4 CCiIF CMS=10 CMS=11 OCiREF CCRx=7 CMS=10 or 11 CCiIF OCiREF ‘1’ CCRx=8 CMS=01 CCiIF CMS=10 CMS=11 OCiREF ‘1’ CCRx>8 CMS=01 CCiIF CMS=10 CMS=11 ‘0’...

  • Page 174: Figure 72. Example Of One-Pulse Mode

    16-bit advanced control timer (TIM1) RM0016 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay.
  • Page 175 RM0016 16-bit advanced control timer (TIM1) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler) as follows: ● The t is defined by the value written in the TIM1_CCR1 register DELAY ●...

  • Page 176: Figure 73. Complementary Output With Deadtime Insertion

    16-bit advanced control timer (TIM1) RM0016 Deadtime insertion is enabled by setting the CCi E and CCi NE bits, and the MOE bit if the break circuit is present. Each channel embeds an 8-bit deadtime generator. It generates two outputs: OCi and OCi N from a reference waveform, OCi REF. If OCi and OCi N are active high: ●...
  • Page 177 RM0016 16-bit advanced control timer (TIM1) Re-directing OCiREF to OCi or OCiN In output mode (forced, output compare, or PWM), OCiREF can be re-directed to the OCi or OCiN outputs by configuring the CCiE and CCiNE bits in the corresponding TIM1_CCERi registers.

  • Page 178: Using The Break Function

    16-bit advanced control timer (TIM1) RM0016 Figure 76. Six-step generation, COM example (OSSR = 1) (CCRx) counter (CNT) OCiREF Write COMG to 1 Commutation (COM) CCiE=1 Write CCiE to 0 CCiE=1 CCiNE=0 CCiNE=0 OCiM=110 (PWM1) OCiM=100 EXAMPLE 1 OCiN CCiE=1 Write CCiNE to 1 CCiE=0 CCiNE=0...

  • Page 179: Figure 77. Behavior Of Outputs In Response To A Break (Channel Without Complementary Output)

    RM0016 16-bit advanced control timer (TIM1) When a break occurs (selected level on the break input): ● The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state, or reset state (selected by the OSSI bit). This happens even if the MCU oscillator is off. ●...

  • Page 180: Figure 78. Behavior Of Outputs In Response To A Break (Tim1 Complementary Outputs)

    16-bit advanced control timer (TIM1) RM0016 Figure 78 shows an example of behavior of the complementary outputs (TIM1 only) in response to a break. Figure 78. Behavior of outputs in response to a break (TIM1 complementary outputs) BREAK (MOE (OCiN not implemented, CCiP=1, OISi=0) delay delay delay...

  • Page 181: Clearing The Ociref Signal On An External Event

    RM0016 16-bit advanced control timer (TIM1) 17.5.9 Clearing the OCiREF signal on an external event The OCiREF signal of a given channel can be cleared when a high level is detected on ETRF (if OCiCE =1 in the TIM1_CCMRi registers, one enable bit per channel). The OCiREF signal remains low until the next UEV occurs.

  • Page 182: Encoder Interface Mode

    16-bit advanced control timer (TIM1) RM0016 17.5.10 Encoder interface mode Encoder interface mode is typically used for motor control. It can be selected by writing: ● SMS = 001 in the TIM1_SMCR register if the counter is counting on TI2 edges only ●...

  • Page 183: Figure 80. Example Of Counter Operation In Encoder Interface Mode

    RM0016 16-bit advanced control timer (TIM1) Figure 80 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near one of the switching points. In the example below, configuration is as follows: ●...

  • Page 184: Tim1 Interrupts

    16-bit advanced control timer (TIM1) RM0016 When the timer is configured in encoder interface mode, it provides information on the current position of the sensors. Dynamic information, such as speed, acceleration, and slowdown, can be obtained by measuring the period between two encoder events using a second timer configured in capture mode.

  • Page 185: Tim1 Registers

    RM0016 16-bit advanced control timer (TIM1) 17.7 TIM1 registers 17.7.1 Control register 1 (TIM1_CR1) Address offset: 0x00 Reset value: 0x00 ARPE CMS[1:0] UDIS Bit 7 ARPE: Auto-reload preload enable 0: TIM1_ARR register is not buffered through a preload register. It can be written directly 1: TIM1_ARR register is buffered through a preload register Bits 6:5 CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode.
  • Page 186 16-bit advanced control timer (TIM1) RM0016 Bit 1 UDIS: Update disable. 0: A UEV is generated as soon as a counter overflow occurs, a software update is generated, or a hardware reset is generated by the clock/trigger mode controller. Buffered registers are then loaded with their preload values.

  • Page 187: Control Register 2 (Tim1_Cr2)

    RM0016 16-bit advanced control timer (TIM1) 17.7.2 Control register 2 (TIM1_CR2) Address offset: 0x01 Reset value: 0x00 MMS[2:0] COMS CCPC Reserved Reserved Reserved Bit 7 Reserved Bits 6:4 MMS[2:0]: Master mode selection These bits select the information to be sent in master mode to the ADC or to the other timers for synchronization (TRGO).

  • Page 188: Slave Mode Control Register (Tim1_Smcr)

    16-bit advanced control timer (TIM1) RM0016 17.7.3 Slave mode control register (TIM1_SMCR) Address offset: 0x02 Reset value: 0x00 TS[2:0] SMS[2:0] Reserved Bit 7 MSM: Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between TIM1 and another timer (through TRGO).

  • Page 189: External Trigger Register (Tim1_Etr)

    RM0016 16-bit advanced control timer (TIM1) 17.7.4 External trigger register (TIM1_ETR) Address offset: 0x03 Reset value: 0x00 ETPS[1:0] ETF[3:0] Bit 7 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 6 ECE: External clock enable This bit enables external clock mode 2.
  • Page 190 16-bit advanced control timer (TIM1) RM0016 Bits 3:0 ETF: External trigger filter. This bitfield defines the frequency used to sample the ETRP signal and the length of the digital filter applied to it. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, sampling is done at f MASTER...

  • Page 191: Interrupt Enable Register (Tim1_Ier)

    RM0016 16-bit advanced control timer (TIM1) 17.7.5 Interrupt enable register (TIM1_IER) Address offset: 0x04 Reset value: 0x00 COMIE CC4IE CC3IE CC2IE CC1IE Bit 7 BIE: Break interrupt enable 0: Break interrupt disabled 1: Break interrupt enabled Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Bit 5 COMIE: Commutation interrupt enable...

  • Page 192: Status Register 1 (Tim1_Sr1)

    16-bit advanced control timer (TIM1) RM0016 17.7.6 Status register 1 (TIM1_SR1) Address offset: 0x05 Reset value: 0x00 COMIF CC4IF CC3IF CC2IF CC1IF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bit 7 BIF: Break interrupt flag This flag is set by hardware as soon as the break input goes active. It can be cleared by software if the break input is not active.

  • Page 193: Status Register 2 (Tim1_Sr2)

    RM0016 16-bit advanced control timer (TIM1) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update has occurred 1: Update interrupt pending. This bit is set by hardware when the registers are updated: –...

  • Page 194: Event Generation Register (Tim1_Egr)

    16-bit advanced control timer (TIM1) RM0016 17.7.8 Event generation register (TIM1_EGR) Address offset: 0x07 Reset value: 0x00 COMG CC4G CC3G CC2G CC1G Bit 7 BG: Break generation This bit is set by software to generate an event. It is automatically cleared by hardware. 0: No action 1: A break event is generated.

  • Page 195: Capture/Compare Mode Register 1 (Tim1_Ccmr1)

    RM0016 16-bit advanced control timer (TIM1) 17.7.9 Capture/compare mode register 1 (TIM1_CCMR1) Address offset: 0x08 Reset value: 0x00 This channel can be used in input (capture mode) or in output (compare mode). The direction of the channel is defined by configuring the CC1S bits. All the other bits of this register have a different function in input and output mode.
  • Page 196 16-bit advanced control timer (TIM1) RM0016 Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIM1_CCR1 disabled. TIM1_CCR1 can be written at anytime. The new value is taken into account immediately. 1: Preload register on TIM1_CCR1 enabled. Read/write operations access the preload register. TIM1_CCR1 preload value is loaded in the shadow register at each UEV.
  • Page 197 RM0016 16-bit advanced control timer (TIM1) Channel configured in input IC1F[3:0] IC1PSC[1:0] CC1S[1:0] Bits 7:4 IC1F[3:0]: Input capture 1 filter This bitfield defines f , the frequency used to sample TI1 input and the length of the digital SAMPLING filter applied to TI1. The digital filter is made of an event counter in which N events are needed to validate a transition on the output: 0000: No filter, f SAMPLING...

  • Page 198: Capture/Compare Mode Register 2 (Tim1_Ccmr2)

    16-bit advanced control timer (TIM1) RM0016 17.7.10 Capture/compare mode register 2 (TIM1_CCMR2) Address offset: 0x09 Reset value: 0x00 Channel configured in output OC2CE OC2M[2:0] OC2PE OC2FE CC2S[1:0] Bit 7 OC2CE: Output compare 2 clear enable Bits 6:4 OC2M(2:0]: Output compare 2 mode Bit 3 OC2PE: Output compare 2 preload enable Bit 2 OC2FE: Output compare 2 fast enable Bits 1:0 CC2S[1:0]: Capture/compare 2 selection...

  • Page 199: Capture/Compare Mode Register 3 (Tim1_Ccmr3)

    RM0016 16-bit advanced control timer (TIM1) 17.7.11 Capture/compare mode register 3 (TIM1_CCMR3) Address offset: 0x0A Reset value: 0x00 Refer to the CCMR1 register description above. Channel configured in output OC3CE OC3M[2:0] OC3PE OC3FE CC3S[1:0] Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M[2:0]: Output compare 3 mode Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable...

  • Page 200: Capture/Compare Mode Register 4 (Tim1_Ccmr4)

    16-bit advanced control timer (TIM1) RM0016 17.7.12 Capture/compare mode register 4 (TIM1_CCMR4) Address offset: 0xB Reset value: 0x00 Refer to the CCMR1 register description above. Channel configured in output OC4CE OC4M[2:0] OC4PE OC4FE CC4S[1:0] Bit 7 OC4CE: Output compare 4 clear enable Bits 6:4 OC4M[2:0]: Output compare 4 mode Bit 3 OC4PE: Output compare 4 preload enable Bit 2 OC4FE: Output compare 4 fast enable...

  • Page 201: Capture/Compare Enable Register 1 (Tim1_Ccer1)

    RM0016 16-bit advanced control timer (TIM1) 17.7.13 Capture/compare enable register 1 (TIM1_CCER1) Address offset: 0x0C Reset value: 0x00 CC2NP CC2NE CC2P CC2E CC1NP CC1NE CC1P CC1E Bit 7 CC2NP: Capture/compare 2 complementary output polarity Refer to CC1NP description. Bit 6 CC2NE: Capture/compare 2 complementary output enable Refer to CC1NE description.

  • Page 202: Table 38. Output Control For Complementary Oci And Ocin Channels With Break Feature

    16-bit advanced control timer (TIM1) RM0016 Bit 0 CC1E: Capture/compare 1 output enable CC1 channel is configured as output: 0: Off - OC1 is not active. OC1 level is then a function of the MOE, OSSI, OSSR, OIS1, OIS1N and CC1NE bits.
  • Page 203 RM0016 16-bit advanced control timer (TIM1) Table 38. Output control for complementary OCi and OCiN channels with break feature Control bits Output states OSSI OSSR CCiE CCiNE OCiN Output disabled (not driven by the timer) Off state (output enabled with inactive state) Asynchronously: OCi = CCiP and OCiN = CCiNP Then if the clock is present: OCi = OISi and OCiN = OISiN after a deadtime, assuming that OISi and OISiN do not correspond...

  • Page 204: Capture/Compare Enable Register 2 (Tim1_Ccer2)

    16-bit advanced control timer (TIM1) RM0016 17.7.14 Capture/compare enable register 2 (TIM1_CCER2) Address offset: 0x0D Reset value: 0x00 CC4P CC4E CC3NP CC3NE CC3P CC3E Reserved Bits 7:6 Reserved Bit 5 CC4P: Capture/compare 4 output polarity Refer to CC1P description. Bit 4 CC4E: Capture/compare 4 output enable Refer to CC1E description.

  • Page 205: Counter Low (Tim1_Cntrl)

    RM0016 16-bit advanced control timer (TIM1) 17.7.16 Counter low (TIM1_CNTRL) Address offset: 0x0F Reset value: 0x00 CNT[7:0] Bits 7:0 CNT[7:0]: Counter value (LSB). 17.7.17 Prescaler high (TIM1_PSCRH) Address offset: 0x10 Reset value: 0x00 PSC[15:8] PSC[15:8]: Prescaler value (MSB) The prescaler value divides the CK_PSC clock frequency. The counter clock frequency f CK_CNT equal to f / (PSCR[15:0]+1).

  • Page 206: Auto-Reload Register High (Tim1_Arrh)

    16-bit advanced control timer (TIM1) RM0016 17.7.19 Auto-reload register high (TIM1_ARRH) Address offset: 0x12 Reset value: 0xFF ARR[15:8] Bits 7:0 ARR[15:8]: Auto-reload value (MSB) ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 17.3: TIM1 time base unit on page 139 for more details about ARR update and behavior.

  • Page 207: Capture/Compare Register 1 High (Tim1_Ccr1H)

    RM0016 16-bit advanced control timer (TIM1) 17.7.22 Capture/compare register 1 high (TIM1_CCR1H) Address offset: 0x15 Reset value: 0x00 CCR1[15:8] Bits 7:0 CCR1[15:8]: Capture/compare 1 value (MSB) If the CC1 channel is configured as output (CC1S bits in TIM1_CCMR1 register): The value of CCR1 is loaded permanently into the actual capture/compare 1 register if the preload feature is enabled (OC1PE bit in TIMx_CCMR1).

  • Page 208: Capture/Compare Register 2 High (Tim1_Ccr2H)

    16-bit advanced control timer (TIM1) RM0016 17.7.24 Capture/compare register 2 high (TIM1_CCR2H) Address offset: 0x17 Reset value: 0x00 CCR2[15:8] Bits 7:0 CCR2[15:8]: Capture/compare 2 value (MSB) If the CC2 channel is configured as output (CC2S bits in TIM1_CCMR2 register): The value of CCR2 is loaded permanently into the actual capture/compare 2 register if the preload feature is not enabled (OC2PE bit in TIM1_CCMR2).

  • Page 209: Capture/Compare Register 3 High (Tim1_Ccr3H)

    RM0016 16-bit advanced control timer (TIM1) 17.7.26 Capture/compare register 3 high (TIM1_CCR3H) Address offset: 0x19 Reset value: 0x00 CCR3[15:8] Bits 7:0 CCR3[15:8]: Capture/compare value (MSB) If the CC3 channel is configured as output (CC3S bits in TIM1_CCMR3 register): The value of CCR3 is loaded permanently into the actual capture/compare 3 register if the preload feature is not enabled (OC3PE bit in TIM1_CCMR3).

  • Page 210: Capture/Compare Register 4 High (Tim1_Ccr4H)

    16-bit advanced control timer (TIM1) RM0016 17.7.28 Capture/compare register 4 high (TIM1_CCR4H) Address offset: 0x1B Reset value: 0x00 CCR4[15:8] Bits 7:0 CCR4[15:8]: Capture/compare value (MSB) If the CC4 channel is configured as output (CC4S bits in TIM1_CCMR4 register): The value of CCR4 is loaded permanently into the actual capture/compare 4 register if the preload feature is not enabled (OC4PE bit in TIM1_CCMR4).

  • Page 211: Break Register (Tim1_Bkr)

    RM0016 16-bit advanced control timer (TIM1) 17.7.30 Break register (TIM1_BKR) Address offset: 0x1D Reset value: 0x00 OSSR OSSI LOCK Bit 7 MOE: Main output enable This bit is cleared asynchronously by hardware as soon as the break input is active. It is set by software or automatically depending on the AOE bit.

  • Page 212: Deadtime Register (Tim1_Dtr)

    16-bit advanced control timer (TIM1) RM0016 Bits 1:0 LOCK[1:0]: Lock configuration These bits offer a write protection against software errors. 00: LOCK off - No bits are write protected 01: LOCK level 1 - OISi bit in TIM1_OISR register and BKE/BKP/AOE bits in TIM1_BKR register can no longer be written.

  • Page 213: Output Idle State Register (Tim1_Oisr)

    RM0016 16-bit advanced control timer (TIM1) 17.7.32 Output idle state register (TIM1_OISR) Address offset: 0x1F Reset value: 0x00 OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 Reserved Bit 7 Reserved, forced by hardware to 0 Bit 6 OIS4: Output idle state 4 (OC4 output) Refer to OIS1 bit Bit 5 OIS3N: Output idle state 3 (OC3N output) Refer to OIS1N bit...

  • Page 214: Tim1 Register Map And Reset Values

    16-bit advanced control timer (TIM1) RM0016 17.7.33 TIM1 register map and reset values Table 39. TIM1 register map Address offset Register name TIM1_CR1 ARPE CMS1 CMS0 UDIS 0x00 Reset value TIM1_CR2 MMS2 MMS1 MMS0 COMS CCPC 0x01 Reset value TIM1_SMCR SMS2 SMS1 SMS0...
  • Page 215 RM0016 16-bit advanced control timer (TIM1) Table 39. TIM1 register map (continued) Address offset Register name TIM1_ARRH ARR15 ARR14 ARR13 ARR12 ARR11 ARR10 ARR9 ARR8 0x12 Reset value TIM1_ARRL ARR7 ARR6 ARR5 ARR4 ARR3 ARR2 ARR1 ARR0 0x13 Reset value TIM1_RCR REP7 REP6...

  • Page 216: 16-Bit General Purpose Timers (Tim2, Tim3, Tim5)

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) 18.1 Introduction This chapter describes TIM2 and TIM3 which are identical timers, with the exception that TIM2 has three channels and TIM3 has two channels. TIM5 is also described below. It is identical to TIM2 except that it has two additional registers to support timer synchronization and chaining.

  • Page 217: Tim5 Main Features

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) 18.3 TIM5 main features TIM5 features include: ● 16-bit up counting auto-reload counter. ● 4-bit programmable prescaler allowing the counter clock frequency to be divided “on the fly” by any power of 2 from 1 to 32768. ●...

  • Page 218: Time Base Unit

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 Figure 83. TIM5 block diagram MASTER TRGO to TIM1/TIM6 timers TIM1_ETR CLOCK/TRIGGER CONTROLLER INTx TRGO from other TIM timers Clock/reset/enable TIME BASE UNIT CK_CNT CK_PSC Prescaler UP-DOWN COUNTER Auto-reload register CAPTURE COMPARE ARRAY CC1I IC1PS OC1REF...

  • Page 219: Clock/Trigger Controller

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) For more details refer to Section 17.3: TIM1 time base unit on page 139. Prescaler The prescaler implementation is as follows: ● The prescaler is based on a 16-bit counter controlled through a 4-bit register (in the TIMx_PSCR register).

  • Page 220: Capture/Compare Channels

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 18.4.3 Capture/compare channels Input stage Refer to Section 17.5: TIM1 capture/compare channels on page 163. There are two input channels, as shown in Figure 85: Input stage block diagram. Figure 85. Input stage block diagram TI1F_ED to clock/trigger controller TI1FP1...

  • Page 221: Tim2/Tim3/Tim5 Interrupts

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) Output stage Refer to Section 17.5.4: Output stage on page 168, Section 17.5.5: Forced output mode on page 169, Section 17.5.7: PWM mode on page 171. Note: As the clock/trigger controller and the associated TIMx_CR2 and TIMx_SMCR registers are not implemented in TIM2/TIM3, the one-pulse mode (described in Section 17.5.7: PWM mode) is not available in TIM2/TIM3.
  • Page 222 16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 The different interrupt sources can be also generated by software using the corresponding bits in the TIMx_EGR register. 222/449 Doc ID 14587 Rev 8...

  • Page 223: Tim2/Tim3/Tim5 Registers

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) 18.6 TIM2/TIM3/TIM5 registers 18.6.1 Control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x00 ARPE UDIS Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered through a preload register. It can be written directly 1: TIMx_ARR register is buffered through a preload register Bits 6:4 Reserved Bit 3 OPM: One-pulse mode...

  • Page 224: Control Register 2 (Tim5_Cr2)

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 18.6.2 Control register 2 (TIM5_CR2) Address offset: 0x01 Reset value: 0x00 MMS[2:0] Reserved Reserved Note: This register is only available in TIM5, see Table 42 on page 241. Bit 7 Reserved, must be kept cleared Bits 6:4 MMS[2:0]: Master mode selection These bits select the information to be sent in master mode to TIM1 and TIM2for synchronization (TRGO).

  • Page 225: Slave Mode Control Register (Tim5_Smcr)

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) 18.6.3 Slave mode control register (TIM5_SMCR) Address offset: 0x02 Reset value: 0x00 TS[2:0] SMS[2:0] Reserved Note: This register is only available in TIM5, see Table 42 on page 241. Bit 7 MSM Master/slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between timers (through TRGO).

  • Page 226: Interrupt Enable Register (Timx_Ier)

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 18.6.4 Interrupt enable register (TIMx_IER) Address offset: 0x01 or 0x03 (TIM2), 0x01 (TIM3), 0x03 (TIM5); for TIM2 address see Section Reset value: 0x00 CC3IE CC2IE CC1IE Reserved Reserved Bits 7 Reserved Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Note: In TIM2/TIM3 this bit is reserved.

  • Page 227: Status Register 1 (Timx_Sr1)

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) 18.6.5 Status register 1 (TIMx_SR1) Address offset: 0x02 or 0x04 (TIM2), 0x02 (TIM3), 0x04 (TIM5); for TIM2 address see Section Reset value: 0x00 CC3IF CC2IF CC1IF Reserved Reserved rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bit 7 Reserved Bit 6 TIF: Trigger interrupt flag...

  • Page 228: Status Register 2 (Timx_Sr2)

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 18.6.6 Status register 2 (TIMx_SR2) Address offset: 0x03 or 0x05 (TIM2), 0x03 (TIM3), 0x05 (TIM5); for TIM2 address see Section Reset value: 0x00 CC3OF CC2OF CC1OF Reserved Reserved rc_w0 rc_w0 rc_w0 Bits 7:4 Reserved Bit 3 CC3OF: Capture/compare 3 overcapture flag Refer to CC1OF description Bit 2 CC2OF: Capture/compare 2 overcapture flag...

  • Page 229: Event Generation Register (Timx_Egr)

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) 18.6.7 Event generation register (TIMx_EGR) Address offset: 0x04 or 0x06 (TIM2), 0x04 (TIM3), 0x06 (TIM5); for TIM2 address see Section Reset value: 0x00 CC2G CC3G CC1G Reserved Reserved Bit 7 Reserved Bit 6 TG: Trigger generation This bit is set by software to generate an event.

  • Page 230: Capture/Compare Mode Register 1 (Timx_Ccmr1)

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 18.6.8 Capture/compare mode register 1 (TIMx_CCMR1) The channel can be used in input (capture mode) or in output (compare mode). The direction of the channel is defined by configuring the CC1S bits. All the other bits of this register have a different function in input and in output mode.
  • Page 231 RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) Bits 1:0 CC1S[1:0]: Capture/compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1FP1 10: CC1 channel is configured as input, IC1 is mapped on TI2FP1 11: CC1 channel is configured as input, IC1 is mapped on TRC.

  • Page 232: Capture/Compare Mode Register 2 (Timx_Ccmr2)

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 Bits 1:0 CC1S[1:0]: Capture/compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1FP1 10: CC1 channel is configured as input, IC1 is mapped on TI2FP1 11: Reserved Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER1 and...

  • Page 233: Capture/Compare Mode Register 3 (Timx_Ccmr3)

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) Channel configured in input IC2F[3:0] IC2PSC[1:0] CC2S[1:0] Bits 7:4 IC2F[3:0]: Input capture 2 filter Bits 3:2 IC2PCS[1:0]: Input capture 2 prescaler Bits 1:0 CC2S[1:0]: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2FP2 10: CC2 channel is configured as input, IC2 is mapped on TI1FP2...

  • Page 234: Capture/Compare Enable Register 1 (Timx_Ccer1)

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 Channel configured in input IC3F[3:0] IC3PSC[1:0] CC3S[1:0] Note: This register is not available in TIM3. Bits 7:4 IC3F[3:0] Input capture 3 filter Bits 3:2 IC3PSC(1:0]: Input capture 3 prescaler Bits 1:0 CC3S[1:0]: Capture/compare 3 selection This bitfield defines the direction of the channel (input/output) as well as the used input.

  • Page 235: Capture/Compare Enable Register 2 (Timx_Ccer2)

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) Bit 0 CC1E: Capture/Compare 1 output Enable. CC1 channel configured as output: 0: Off - OC1 is not active. 1: On - OC1 signal is output on the corresponding output pin. CC1 channel configured as input: In this case, this bit determines if a capture of the counter value can be made in the input capture/compare register 1 (TIMx_CCR1) or not.

  • Page 236: Counter Low (Timx_Cntrl)

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 18.6.14 Counter low (TIMx_CNTRL) Address offset: 0x0B or 0x0D (TIM2), 0x09 (TIM3), 0x0D (TIM5); for TIM2 address see Section Reset value: 0x00 CNT[7:0] Bits 7:0 CNT[7:0]: Counter value (LSB) 18.6.15 Prescaler register (TIMx_PSCR) Address offset: 0x0C or 0x0E (TIM2), 0x0A (TIM3), 0x0E (TIM5);...

  • Page 237: Auto-Reload Register Low (Timx_Arrl)

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) 18.6.17 Auto-reload register low (TIMx_ARRL) Address offset: 00x0E or 0x10 (TIM2), 0x0C (TIM3), 0x10 (TIM5); for TIM2 address see Section Reset value: 0xFF ARR[7:0] Bits 7:0 ARR[7:0]: Auto-reload value (LSB) 18.6.18 Capture/compare register 1 high (TIMx_CCR1H) Address offset: 00x0F or 0x11 (TIM2), 0x0D (TIM3), 0x11 (TIM5);...

  • Page 238: Capture/Compare Register 1 Low (Timx_Ccr1L)

    16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 18.6.19 Capture/compare register 1 low (TIMx_CCR1L) Address offset: 00x10 or 0x12 (TIM2), 0x0E (TIM3), 0x12 (TIM5); for TIM2 address see Section Reset value: 0x00 CCR1[7:0] Bits 7:0 CCR1[7:0]: Capture/compare 1 value (LSB) 18.6.20 Capture/compare register 2 high (TIMx_CCR2H) Address offset: 00x11 or 0x13 (TIM2), 0x0F (TIM3), 0x13 (TIM5);...

  • Page 239: Capture/Compare Register 3 High (Timx_Ccr3H)

    Bits 7:0 CCR3[7:0]: Capture/compare value (LSB) TIM2/TIM3/TIM5 register map and reset values In some STM8S and STM8A devices, TIM2 register locations at offset 0x01 and 0x02 are reserved. In this case the TIM2_IER and subsequent registers in the TIM2 block are offset by 2 more bytes.
  • Page 240 16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 Table 40. TIM2 register map (continued) Address offset Register name (product dependent) TIM2_SR2 CC3OF CC2OF CC1OF 0x03 0x05 Reset value TIM2_EGR CC3G CC2G CC1G 0x04 0x06 Reset value TIM2_CCMR1 OC1M2 OC1M1 OC1M0 OC1PE CC1S1 CC1S0...

  • Page 241: Table 41. Tim3 Register Map

    RM0016 16-bit general purpose timers (TIM2, TIM3, TIM5) Table 41. TIM3 register map Address Register name offset TIM3_CR1 ARPE UDIS 0x00 Reset value TIM3_IER CC2IE CC1IE 0x01 Reset value TIM3_SR1 CC2IF CC1IF 0x02 Reset value TIM3_SR2 CC2OF CC1OF 0x03 Reset value TIM3_EGR CC2G CC1G...
  • Page 242 16-bit general purpose timers (TIM2, TIM3, TIM5) RM0016 Table 42. TIM5 register map (continued) Address Register name TIM5_IER CC3IE CC2IE CC1IE 0x03 Reset value TIM5_SR1 CC3IF CC2IF CC1IF 0x04 Reset value TIM5_SR2 CC3OF CC2OF CC1OF 0x05 Reset value TIM5_EGR CC3G CC2G CC1G 0x06...

  • Page 243: 8-Bit Basic Timer (Tim4, Tim6)

    RM0016 8-bit basic timer (TIM4, TIM6) 8-bit basic timer (TIM4, TIM6) 19.1 Introduction The timer consists of an 8-bit auto-reload up-counter driven by a programmable prescaler. It can be used for time base generation, with interrupt generation on timer overflow. TIM6 is implemented with the clock/trigger controller for timer synchronization and chaining.

  • Page 244: Tim4 Main Features

    8-bit basic timer (TIM4, TIM6) RM0016 19.2 TIM4 main features The main features include: ● 8-bit auto-reload up counter ● 3-bit programmable prescaler which allows dividing (also “on the fly”) the counter clock frequency by 1, 2, 4, 8, 16, 32, 64 and 128. ●...

  • Page 245: Tim4/Tim6 Registers

    RM0016 8-bit basic timer (TIM4, TIM6) 19.6 TIM4/TIM6 registers 19.6.1 Control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x00 ARPE UDIS Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIM4_ARR register is not buffered through a preload register. It can be written directly 1: TIM4_ARR register is buffered through a preload register Bits 6:4 Reserved, must be kept cleared Bit 3 OPM: One-pulse mode...

  • Page 246: Control Register 2 (Tim6_Cr2)

    8-bit basic timer (TIM4, TIM6) RM0016 19.6.2 Control register 2 (TIM6_CR2) Address offset: 0x01 Reset value: 0x00 MMS[2:0] Reserved Reserved Note: This register is not available in TIM4. Bit 7 Reserved, must be kept cleared Bits 6:4 MMS[2:0]: Master mode selection These bits are used to select the information to be sent in master mode to for synchronization (TRGO).

  • Page 247: Interrupt Enable Register (Timx_Ier)

    RM0016 8-bit basic timer (TIM4, TIM6) Bits 6:4 TS[2:0]: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 000: Reserved 001: reserved 010: Internal trigger ITR2 connected to TIM5 TRGO 011: Internal trigger ITR3 connected to TIM1 TRGO 100: Reserved 101: Reserved 110: Reserved...

  • Page 248: Status Register 1 (Timx_Sr)

    8-bit basic timer (TIM4, TIM6) RM0016 19.6.5 Status register 1 (TIMx_SR) Address offset: 0x02 or 0x04 (TIM4), 0x04 (TIM6); for TIM4 address see Section 19.6.10 Reset value: 0x00 Reserved Reserved rc_w0 rc_w0 Bit 7 Reserved, must be kept cleared Bit 6 TIF: Trigger interrupt flag. This flag is set by hardware on a trigger event (the active edge is detected on the TRGI signal, both edges are detected if gated mode is selected).

  • Page 249: Counter (Timx_Cntr)

    RM0016 8-bit basic timer (TIM4, TIM6) 19.6.7 Counter (TIMx_CNTR) Address offset: 0x04 or 0x06 (TIM4), 0x06 (TIM6); for TIM4 address see Section 19.6.10 Reset value: 0x00 CNT[7:0] Bits 7:0 CNT[7:0]: Counter value Doc ID 14587 Rev 8 249/449...

  • Page 250: Prescaler Register (Timx_Pscr)

    8-bit basic timer (TIM4, TIM6) RM0016 19.6.8 Prescaler register (TIMx_PSCR) Address offset: 0x05 or 0x07 (TIM4), 0x07 (TIM6); for TIM4 address see Section 19.6.10 Reset value: 0x00 PSC[2:0] Reserved Bits 7:3 Reserved, must be kept cleared Bits 2:0 PSC[2:0]: Prescaler value The prescaler value divides the CK_PSC clock frequency.

  • Page 251: Tim4/Tim6 Register Map And Reset Values

    19.6.10 TIM4/TIM6 register map and reset values In some STM8S and STM8A devices, TIM4 register locations at offset 0x01 and 0x02 are reserved. In this case the TIM4_IER and subsequent registers in the TIM4 block are offset by 2 more bytes. Refer to the datasheet for the product-specific register map.
  • Page 252 8-bit basic timer (TIM4, TIM6) RM0016 Table 44. TIM6 register map (continued) Address Register name offset TIM6_PSCR PSC2 PSC1 PSC0 0x07 Reset value TIM6_ARR ARR7 ARR6 ARR5 ARR4 ARR3 ARR2 ARR1 ARR0 0x08 Reset value 252/449 Doc ID 14587 Rev 8...

  • Page 253: Serial Peripheral Interface (Spi)

    RM0016 Serial peripheral interface (SPI) Serial peripheral interface (SPI) 20.1 Introduction The serial peripheral interface (SPI) allows half/ full duplex, synchronous, serial communication with external devices. The interface can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface is also capable of operating in multi-master configuration.

  • Page 254: Spi Functional Description

    Serial peripheral interface (SPI) RM0016 20.3 SPI functional description 20.3.1 General description The block diagram of the SPI is shown in Figure Figure 91. SPI block diagram ADDRESS AND DATA BUS READ RX BUFFER MOSI TXIE RXIE WKIE SHIFT REGISTER MISO LSBFirst OVR MOD...

  • Page 255: Figure 92. Single Master/ Single Slave Application

    RM0016 Serial peripheral interface (SPI) Note: When using the SPI in High-speed mode, the I/Os where SPI outputs are connected should be programmed as fast slope outputs in order to be able to reach the expected bus speed. Figure 92. Single master/ single slave application SLAVE MASTER MSBit...
  • Page 256 Serial peripheral interface (SPI) RM0016 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA bits. The CPOL (clock polarity) bit controls the steady state value of the clock when no data is being transferred.

  • Page 257: Figure 93. Data Clock Timing Diagram

    RM0016 Serial peripheral interface (SPI) Figure 93. Data clock timing diagram CPHA =1 CPOL = 1 CPOL = 0 Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6 Bit 5 MISO Bit 4 Bit3 Bit 2 Bit 1 LSBit MSBit Bit 6...

  • Page 258: Configuring The Spi In Slave Mode

    Serial peripheral interface (SPI) RM0016 20.3.2 Configuring the SPI in slave mode In slave configuration, the serial clock is received on the SCK pin from the master device. The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data transfer rate.

  • Page 259: Configuring The Spi For Simplex Communications

    RM0016 Serial peripheral interface (SPI) 20.3.4 Configuring the SPI for simplex communications The SPI is capable of operating in simplex mode in 2 configurations. ● 1 clock and 1 bidirectional data wire ● 1 clock and 1 data wire (Receive-only or Transmit-only) 1 clock and 1 bidirectional data wire This mode is enabled by setting the BDM bit in the SPI_CR2 register.
  • Page 260 Serial peripheral interface (SPI) RM0016 ● In unidirectional receive-only mode (BDM = 0 and RXONLY = 1) – The sequence begins as soon as the bit SPE = 1 – Only the receiver is activated and the received data on MISO pin is shifted in serially to the 8-bit shift register and then parallel loaded into the SPI_DR register (Rx Buffer).
  • Page 261 RM0016 Serial peripheral interface (SPI) Handling data transmission and reception The TXE flag (Tx buffer empty) is set when the data is transferred from the Tx buffer to the shift register. It indicates that the internal Tx buffer is ready to be loaded with the next data. An interrupt can be generated if TXIE bit in the SPI_ICR register is set.

  • Page 262: Figure 94. Txe/Rxne/Bsy Behavior In Full Duplex Mode (Rxonly = 0). Case Of Continuous Transfers

    Serial peripheral interface (SPI) RM0016 Figure 94. TXE/RXNE/BSY behavior in full duplex mode (RXONLY = 0). Case of continuous transfers Example in Master Mode with CPOL=1, CPHA=1 DATA1 = 0xF1 DATA2 = 0xF2 DATA3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hw set by hw cleared by sw...

  • Page 263: Figure 96. Txe/Bsy In Master Transmit-Only Mode

    RM0016 Serial peripheral interface (SPI) Transmit-only procedure (BDM = 0 RXONLY = 0) In this mode, the procedure can be reduced as described below and the BSY bit can be used to wait until the effective completion of the transmission (see Figure 94 Figure 95):...

  • Page 264: Figure 97. Txe/Bsy In Slave Transmit-Only Mode (Bdm = 0 And Rxonly = 0)

    Serial peripheral interface (SPI) RM0016 Figure 97. TXE/BSY in slave transmit-only mode (BDM = 0 and RXONLY = 0). Case of continuous transfers Example in slave mode with CPOL=1, CPHA=1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MISO/MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hw...

  • Page 265: Figure 98. Rxne Behavior In Receive-Only Mode (Bdm = 0 And Rxonly = 1)

    RM0016 Serial peripheral interface (SPI) Figure 98. RXNE behavior in receive-only mode (BDM = 0 and RXONLY = 1). Case of continuous transfers Example with CPOL=1, CPHA=1, RXONLY=1 DATA 1 = 0xA1 DATA 2 = 0xA2 DATA 3 = 0xA3 MISO/MOSI (in) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7 set by hw...

  • Page 266: Crc Calculation

    Serial peripheral interface (SPI) RM0016 Figure 99. TXE/BSY behavior when transmitting (BDM = 0 and RXLONY = 0). Case of discontinuous transfers Example with CPOL=1, CPHA = 1 DATA 1 = 0xF1 DATA 2 = 0xF2 DATA 3 = 0xF3 MOSI (out) b0 b1 b2 b3 b4 b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7...

  • Page 267: Status Flags

    RM0016 Serial peripheral interface (SPI) SPI communication using CRC is possible through the following procedure: ● Program the CPOL, CPHA, LSBfirst, BR, SSM, SSI and MSTR values. ● Program the polynomial in the SPI_CRCPR register ● Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This also clears the SPI_RXCRCR and SPI_TXCRCR registers ●...

  • Page 268: Disabling The Spi

    Serial peripheral interface (SPI) RM0016 It is reset: ● when a transfer is finished (except in master mode if the communication is continuous) ● when the SPI is disabled ● when a master mode fault occurs (MODF = 1) When communication is not continuous, the BSY flag is low between each communication. When communication is continuous, in master mode, the BSY flag is kept high during the whole transfers.

  • Page 269: Error Flags

    RM0016 Serial peripheral interface (SPI) In master unidirectional receive-only mode (MSTR = 1, BDM = 0, RXONLY = 1) or bidirectional receive mode (MSTR = 1, BDM = 1, BDOE = 0): This case must be managed in a particular way to ensure that the SPI does not initiate a new transfer: Wait for the second to last occurrence of RXNE = 1 (n-1) Then wait for one SPI clock cycle (using a software loop) before disabling the SPI...

  • Page 270: Spi Low Power Modes

    Serial peripheral interface (SPI) RM0016 Overrun condition An overrun condition occurs, when the master device has sent data bytes and the slave device has not cleared the RXNE bit resulting from the previous data byte transmitted. When an overrun condition occurs: ●...

  • Page 271: Spi Interrupts

    RM0016 Serial peripheral interface (SPI) Restrictions in receive-only modes The wake-up functionality is not guaranteed in receive-only modes (BDM = 0 and RXONLY = 1 or BDM = 1 and BDOE = 0) since the time needed to restore the system clock can be greater than the data reception time.

  • Page 272: Spi Control Register 2 (Spi_Cr2)

    Serial peripheral interface (SPI) RM0016 Bit1 CPOL: Clock polarity 0: SCK to 0 when idle 1: SCK to 1 when idle Bit 0 CPHA: Clock phase 0: The first clock transition is the first data capture edge 1: The second clock transition is the first data capture edge 1.
  • Page 273 RM0016 Serial peripheral interface (SPI) Bit 0 SSI: Internal slave select This bit has effect only when SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O value of the NSS pin is ignored. 0: Slave mode 1: Master mode Doc ID 14587 Rev 8...

  • Page 274: Spi Interrupt Control Register (Spi_Icr)

    Serial peripheral interface (SPI) RM0016 20.4.3 SPI interrupt control register (SPI_ICR) Address offset: 0x02 Reset value: 0x00 TXIE RXIE ERRIE WKIE Reserved Bit 7 TXIE: Tx buffer empty interrupt enable 0: TXE interrupt masked 1: TXE interrupt not masked. This allows an interrupt request to be generated when the TXE flag is set.

  • Page 275: Spi Status Register (Spi_Sr)

    RM0016 Serial peripheral interface (SPI) 20.4.4 SPI status register (SPI_SR) Address offset: 0x03 Reset value: 0x02 MODF CRCERR WKUP RXNE Reserved rc_w0 rc_w0 rc_w0 rc_w0 Bit 7 BSY: Busy flag 0: SPI not busy 1: SPI is busy in communication This flag is set and reset by hardware.

  • Page 276: Spi Data Register (Spi_Dr)

    Serial peripheral interface (SPI) RM0016 20.4.5 SPI data register (SPI_DR) Address offset: 0x04 Reset value: 0x00 DR[7:0] Bits 7:0 DR[7:0]: Data register Byte received or to be transmitted. The data register is split into 2 buffers - one for writing (Transmit buffer) and another one for reading (Receive buffer).

  • Page 277: Spi Tx Crc Register (Spi_Txcrcr)

    RM0016 Serial peripheral interface (SPI) 20.4.8 SPI Tx CRC register (SPI_TXCRCR) Address offset: 0x07Reset value: 0x00 TxCRC[7:0] Bits 7:0 TxCRC[7:0]: Tx CRC register When CRC calculation is enabled, the TxCRC[7:0] bits contain the computed CRC value of the subsequently transmitted bytes. This register is reset when the CRCEN bit of SPI_CR2 is written to 1. The CRC is calculated serially using the polynomial programmed in the SPI_CRCPR register.

  • Page 278: Inter-Integrated Circuit (I 2 C) Interface

    Inter-integrated circuit (I C) interface RM0016 Inter-integrated circuit (I C) interface 21.1 Introduction C (inter-integrated circuit) bus interface serves as an interface between the microcontroller and the serial I C bus. It provides multi-master capability, and controls all I C bus-specific sequencing, protocol, arbitration and timing.

  • Page 279: C General Description

    RM0016 Inter-integrated circuit (I C) interface 21.3 C general description In addition to receiving and transmitting data, this interface converts it from serial to parallel format and vice versa. The interrupts are enabled or disabled by software. The interface is connected to the I C bus by a data pin (SDA) and by a clock pin (SCL).
  • Page 280 Inter-integrated circuit (I C) interface RM0016 Figure 101. I C block diagram DATA REGISTER DATA DATA SHIFT REGISTER CONTROL PEC CALCULATION COMPARATOR OWN ADDRESS REGISTERS PEC REGISTER CLOCK CONTROL CLOCK CONTROL REGISTER (CCR) CONTROL REGISTERS (CR1&CR2) CONTROL STATUS REGISTERS LOGIC (SR1,SR2 &...

  • Page 281: I 2 C Functional Description

    RM0016 Inter-integrated circuit (I C) interface 21.4 C functional description By default the I C interface operates in Slave mode. To switch from default Slave mode to Master mode a Start condition generation is needed. 21.4.1 C slave mode The peripheral input clock must be programmed in the I2C_FREQR register in order to generate correct timings.

  • Page 282: Figure 102. Transfer Sequence Diagram For Slave Transmitter

    Inter-integrated circuit (I C) interface RM0016 Slave transmitter Following the address reception and after clearing ADDR, the slave sends bytes from the DR register to the SDA line via the internal shift register. The slave stretches SCL low until ADDR is cleared and DR filled with the data to be sent (see Transfer sequencing EV1 EV3 in the following figure).

  • Page 283: I 2 C Master Mode

    RM0016 Inter-integrated circuit (I C) interface Figure 103. Transfer sequence diagram for slave receiver 7-bit slave receiver S Address Data1 Data2 DataN ..10-bit slav e receiver S Header Address Data1 DataN ..ai18208 1. Legend: S= Start, S = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge, EVx= Event (with interrupt if ITEVTEN=1) EV1: ADDR =1, cleared by reading SR1 register followed by reading SR3.
  • Page 284 Inter-integrated circuit (I C) interface RM0016 Start condition Setting the START bit causes the interface to generate a Start condition and to switch to Master mode (MSL bit set) when the BUSY bit is cleared. Note: In master mode, setting the START bit causes the interface to generate a Re-Start condition at the end of the current byte transfer.

  • Page 285: Figure 104. Transfer Sequence Diagram For Master Transmitter

    RM0016 Inter-integrated circuit (I C) interface Master transmitter Following the address transmission and after clearing ADDR, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits until the first data byte is written in the DR register, (see Figure 104Transfer sequencing EV8_1).

  • Page 286: Figure 105. Method 1: Transfer Sequence Diagram For Master Receiver

    Inter-integrated circuit (I C) interface RM0016 Master receiver Following the address transmission and after clearing ADDR, the I C interface enters Master Receiver mode. In this mode the interface receives bytes from the SDA line into the DR register via the internal shift register. After each byte the interface generates in sequence: ●...

  • Page 287: Figure 106. Method 2: Transfer Sequence Diagram For Master Receiver When N >2

    RM0016 Inter-integrated circuit (I C) interface EV6_1: no associated flag event, used for 1 byte reception only. Program ACK=0 and STOP=1 after clearing ADDR. EV7: RxNE=1, cleared by reading DR register. EV7_1: RxNE=1, cleared by reading DR register, program ACK=0 and STOP request EV9: ADD10=1, cleared by reading SR1 register followed by writing DR register.

  • Page 288: Figure 107. Method 2: Transfer Sequence Diagram For Master Receiver When N=2

    Inter-integrated circuit (I C) interface RM0016 When 3 bytes remain to be read: ● RxNE = 1 => Nothing (DataN-2 not read). ● DataN-1 received ● BTF = 1 because both shift and data registers are full: DataN-2 in DR and DataN-1 in the shift register =>...

  • Page 289: Error Conditions

    RM0016 Inter-integrated circuit (I C) interface S= Start, S = Repeated Start, P= Stop, A= Acknowledge, NA= Non-acknowledge, EVx= Event (with interrupt if ITEVTEN=1). EV5: SB=1, cleared by reading SR1 register followed by writing the DR register. EV6: ADDR1, cleared by reading SR1 register followed by reading SR3. In 10-bit master receiver mode, this sequence should be followed by writing CR2 with START = 1.
  • Page 290 Inter-integrated circuit (I C) interface RM0016 Bus error (BERR) This error occurs when the I2C interface detects an external stop or a start condition during an address or data transfer. In this case: ● The BERR bit is set and an interrupt is generated if the ITERREN bit is set ●...

  • Page 291: Sda/Scl Line Control

    RM0016 Inter-integrated circuit (I C) interface Underrun error can occur in slave mode when clock stretching is disabled and the I2C interface is transmitting data. The interface has not updated the DR with the next byte (TXE=1), before the clock comes for the next byte. In this case, ●...

  • Page 292: I 2 C Interrupts

    Inter-integrated circuit (I C) interface RM0016 21.6 C interrupts Table 49. C Interrupt requests Enable Exit Exit Event Interrupt event control from from flag Wait Halt Start bit sent (Master) Address sent (Master) or Address matched ADDR (Slave) ITEVTEN 10-bit header sent (Master) ADD10 Stop received (Slave) STOPF...

  • Page 293: I 2 C Registers

    RM0016 Inter-integrated circuit (I C) interface 21.7 C registers 21.7.1 Control register 1 (I2C_CR1) Address offset: 0x00 Reset value: 0x00 NOSTRETCH ENGC Reserved Bit 7 NOSTRETCH: Clock stretching disable (Slave mode) This bit is used to disable clock stretching in slave mode when ADDR or BTF flag is set, until it is reset by software.

  • Page 294: Control Register 2 (I2C_Cr2)

    Inter-integrated circuit (I C) interface RM0016 21.7.2 Control register 2 (I2C_CR2) Address offset: 0x01 Reset value: 0x00 SWRST STOP START Reserved Bit 7 SWRST: Software reset When set, the I2C is at reset state. Before resetting this bit, make sure the I2C lines are released and the bus is free.
  • Page 295 RM0016 Inter-integrated circuit (I C) interface Note: When STOP or START is set, the user must not perform any write access to I2C_CR2 before the control bit is cleared by hardware. Otherwise, a second STOP or START request may occur. Doc ID 14587 Rev 8 295/449...

  • Page 296: Frequency Register (I2C_Freqr)

    Inter-integrated circuit (I C) interface RM0016 21.7.3 Frequency register (I2C_FREQR) Address offset: 0x02 Reset value: 0x00 FREQ[5:0] Reserved Bits 7:6 Reserved Bits 5:0 FREQ[5:0] Peripheral clock frequency. Input clock frequency must be programmed to generate correct timings: The allowed range is between 1 MHz and 24 MHz 000000: not allowed 000001: 1 MHz 000010: 2 MHz...

  • Page 297: Own Address Register Lsb (I2C_Oarl)

    RM0016 Inter-integrated circuit (I C) interface 21.7.4 Own address register LSB (I2C_OARL) Address offset: 0x03 Reset value: 0x00 ADD[7:1] ADD0 Bits 7:1 ADD[7:1] Interface address bits 7:1 of address Bit 0 ADD[0] Interface address 7-bit addressing mode: don’t care 10-bit addressing mode: bit 0 of address 21.7.5 Own address register MSB (I2C_OARH) Address offset: 0x04...

  • Page 298: Data Register (I2C_Dr)

    Inter-integrated circuit (I C) interface RM0016 21.7.6 Data register (I2C_DR) Address offset: 0x06 Reset value: 0x00 DR[7:0] (1)(2)(3) Bits 7:0 DR[7:0]: Data register Byte received or to be transmitted to the bus. – Transmitter mode: Byte transmission starts automatically when a byte is written in the DR register. A continuous transmit stream can be maintained if the next data to be transmitted is put in DR once the transmission is started (TXE=1) –...
  • Page 299 RM0016 Inter-integrated circuit (I C) interface (4)(5) Bit 4 STOPF: Stop detection (Slave mode) 0: No Stop condition detected 1: Stop condition detected – Set by hardware when a Stop condition is detected on the bus by the slave after an acknowledge (if ACK=1).

  • Page 300: Status Register 2 (I2C_Sr2)

    Inter-integrated circuit (I C) interface RM0016 6. The ADD10 bit is not set after a NACK reception. 7. The BTF bit is not set after a NACK reception, or in case of an ARLO event. 8. Due to timing constraints, when in standard mode if CCR is less than 9 (i.e. with peripheral clock below 2 MHz) with and the event interrupt disabled, the following procedure must be followed: MASTER modify the reset sequence in order to insert at least 5 cycles between each operations in the flag clearing sequence.

  • Page 301: Status Register 3 (I2C_Sr3)

    RM0016 Inter-integrated circuit (I C) interface Bit 1 ARLO: Arbitration lost (master mode) 0: No Arbitration lost detected 1: Arbitration lost detected Set by hardware when the interface loses the arbitration of the bus to another master. – Cleared by software writing 0, or by hardware when PE=0. After an ARLO event the interface switches back automatically to Slave mode (MSL=0).

  • Page 302: Interrupt Register (I2C_Itr)

    Inter-integrated circuit (I C) interface RM0016 Note: Reading I2C_SR3 after reading I2C_SR1 clears the ADDR flag, even if the ADDR flag was set after reading I2C_SR1. Consequently, I2C_SR3 must be read only when ADDR is found set in I2C_SR1 or when the STOPF bit is cleared. 21.7.10 Interrupt register (I2C_ITR) Address offset: 0x0A...

  • Page 303: Clock Control Register Low (I2C_Ccrl)

    RM0016 Inter-integrated circuit (I C) interface 21.7.11 Clock control register low (I2C_CCRL) Address offset: 0x02 Reset value: 0x0B CCR[7:0] Bits 7:0 CCR[7:0] Clock control register (Master mode) Controls the SCLH clock in Master mode. – Standard mode: Period(I2C) = 2 * CCR * t MASTER = CCR * t high...

  • Page 304: Clock Control Register High (I2C_Ccrh)

    Inter-integrated circuit (I C) interface RM0016 21.7.12 Clock control register high (I2C_CCRH) Address offset: 0x0C Reset value: 0x00 DUTY CCR[11:8] Reserved Bit 7 F/S: I2C master mode selection 0: Standard mode I2C 1: Fast mode I2C Bit 6 DUTY: Fast mode duty cycle 0: Fast mode t high 1: Fast mode t...

  • Page 305: Trise Register (I2C_Triser)

    RM0016 Inter-integrated circuit (I C) interface Table 50. I2C_CCR values for SCL frequency table (f = 10 MHz or 16 MHz MASTER frequency = 10 MHz = 16 MHz MASTER MASTER Speed Duty Actual % Error I2C_CCR Actual % Error I2C_CCR Duty cycle in Hz...

  • Page 306: C Register Map And Reset Values

    Inter-integrated circuit (I C) interface RM0016 Bits 5:0 TRISE[5:0] Maximum rise time in Fast/Standard mode (Master mode) These bits must be programmed with the maximum SCL rise time given in the I2C bus specification, incremented by 1. For instance: in standard mode, the maximum allowed SCL rise time is 1000 ns. If the value in the I2C_FREQR register = 08h, then t = 125 ns therefore the TRISE[5:0] bits MASTER...

  • Page 307: Universal Asynchronous Receiver Transmitter (Uart)

    22.1 Introduction The UARTs in the STM8S and STM8A microcontroller families (UART1, UART2 or UART3) offer a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format (UART mode). The STM8 UARTs offer a very wide range of baud rates and can also be used for multi-processor communication.

  • Page 308: Uart Main Features

    Universal asynchronous receiver transmitter (UART) RM0016 22.2 UART main features ● Full duplex, asynchronous communications ● NRZ standard format (Mark/Space) ● High-precision baud rate generator system – Common programmable transmit and receive baud rates up to f MASTER ● Programmable data word length (8 or 9 bits) ●...

  • Page 309: Uart Functional Description

    RM0016 Universal asynchronous receiver transmitter (UART) – Noise error – Frame error – Parity error ● 6 interrupt sources with flags – Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error –...

  • Page 310: Figure 110. Uart1 Block Diagram

    Universal asynchronous receiver transmitter (UART) RM0016 The following pin is required to interface in synchronous mode: UART_CK: Transmitter clock output. This pin outputs the transmitter data clock for synchronous transmission (no clock pulses on start bit and stop bit, and a software option to send a clock pulse on the last data bit).

  • Page 311: Figure 111. Uart2 Block Diagram

    RM0016 Universal asynchronous receiver transmitter (UART) Figure 111. UART2 block diagram MCU bus Write Read UART2_DR(DATA REGISTER) Transmit Data Register (TDR) Receive Data Register (RDR) UART2_TX Transmit Shift Register Receive Shift Register UART2_RX UART2_CK CONTROL UART2_CK UART2_GTR GUARD TIME REGISTER UART2_CR5 UART2_CR3 SCEN...

  • Page 312: Figure 112. Uart3 Block Diagram

    Universal asynchronous receiver transmitter (UART) RM0016 Figure 112. UART3 block diagram Write Read UART3_DR (DATA REGISTER) Transmit Data Register (TDR) Receive Data Register (RDR) UART3_TX Transmit Shift Register Receive Shift Register UART3_RX UART3_CR4 UART3_CR3 LBDIEN LBDL LBDF ADD[3:0] LINEN STOP[1:0] UART2_CR1 UARTD WAKE...

  • Page 313: Uart Character Description

    RM0016 Universal asynchronous receiver transmitter (UART) 22.3.1 UART character description Word length may be selected as being either 8 or 9 bits by programming the M bit in the UART_CR1 register (see Figure 113). The UART_TX pin is in low state during the start bit. It is in high state during the stop bit. An Idle character is interpreted as an entire frame of “1”s (the number of “1”...

  • Page 314: Transmitter

    Universal asynchronous receiver transmitter (UART) RM0016 22.3.2 Transmitter The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the UART_CR1 register.

  • Page 315: Figure 114. Configurable Stop Bits

    RM0016 Universal asynchronous receiver transmitter (UART) Figure 114. Configurable stop bits 8-bit Word length (M bit is reset) Possible Next Data Frame Parity Data Frame Next Start Start Stop Bit2 Bit0 Bit1 Bit3 Bit4 Bit5 Bit6 Bit7 CLOCK **** ** LBCL bit controls last data clock pulse a) 1 Stop Bit Possible Next Data Frame...

  • Page 316: Figure 115. Tc/Txe Behavior When Transmitting

    Universal asynchronous receiver transmitter (UART) RM0016 Single byte communication Clearing the TXE bit is always performed by a write to the data register. The TXE bit is set by hardware and it indicates: ● The data has been moved from TDR to the shift register and the data transmission has started.

  • Page 317: Receiver

    RM0016 Universal asynchronous receiver transmitter (UART) Break character Setting the SBK bit transmits a break character. The break frame length depends on the M bit (see Figure 113). If the SBK bit is set to ‘1’ a break character is sent on the UART_TX line after completing the current character transmission.
  • Page 318 Universal asynchronous receiver transmitter (UART) RM0016 Note: If the sequence is not complete, the start bit detection aborts and the receiver returns to the idle state (no flag is set), where it waits for a falling edge. If only 2 out of the 3 bits are at 0 (sampling on the 3 and 7 bits or sampling on the 8 and 10...

  • Page 319: Figure 117. Data Sampling For Noise Detection

    RM0016 Universal asynchronous receiver transmitter (UART) When an overrun error occurs: ● The OR bit is set. ● The RDR content will not be lost. The previous data is available when a read to UART_DR is performed. ● The shift register will be overwritten. The second data received during overrun is lost. ●...

  • Page 320: Table 53. Noise Detection From Sampled Data

    Universal asynchronous receiver transmitter (UART) RM0016 Table 53. Noise detection from sampled data Sampled value NF status Received bit value Data validity Valid Not Valid Not Valid Not Valid Not Valid Not Valid Not Valid Valid When noise is detected in a frame: ●...

  • Page 321: High Precision Baud Rate Generator

    RM0016 Universal asynchronous receiver transmitter (UART) 22.3.4 High precision baud rate generator The receiver and transmitter (Rx and Tx) are both set to the same baud rate programmed by a 16-bit divider UART_DIV according to the following formula: MASTER Tx/ Rx baud rate = UART_DIV The UART_DIV baud rate divider is an unsigned integer, coded in the BRR1 and BRR2 registers as shown in...

  • Page 322: Clock Deviation Tolerance Of The Uart Receiver

    Universal asynchronous receiver transmitter (UART) RM0016 Table 54. Baud rate programming and error calculation Baud = 10 MHz = 16 MHz MASTER MASTER rate Actual % Error UART_DIV BRR1 BRR2 Actual % Error UART_DIV BRR1 BRR2 kbps −0.008% −0.005% 2.399 0x1047 0x04 0x17...

  • Page 323: Parity Control

    RM0016 Universal asynchronous receiver transmitter (UART) Table 56. UART receiver’s tolerance when UART_DIV[3:0] is different from zero M bit NF is an error NF is don’t care 3.33% 3.88% 3.03% 3.53% Note: The values specified in Table 55 Table 56 may slightly differ in the special case when the received frames contain some Idle frames of exactly 10-bit times when M=0 (11-bit times when M=1).

  • Page 324: Multi-Processor Communication

    Universal asynchronous receiver transmitter (UART) RM0016 22.3.7 Multi-processor communication It is possible to perform multi-processor communication with the UART (several UARTs connected in a network). For example, one of the UARTs can be the master, its TX output is connected to the RX input of the other UART. The others are slaves, their respective TX outputs are logically ANDed together and connected to the RX input of the master.

  • Page 325: Lin (Local Interconnection Network) Mode

    RM0016 Universal asynchronous receiver transmitter (UART) It exits from mute mode when an address character is received which matches the programmed address. Then the RWU bit is cleared and subsequent bytes are received normally. The RXNE bit is set for the address character since the RWU bit has been cleared. The RWU bit can be written to 0 or 1 when the receiver buffer contains no data (RXNE=0 in the UART_SR register).

  • Page 326: Uart Synchronous Communication

    Universal asynchronous receiver transmitter (UART) RM0016 22.3.9 UART synchronous communication The UART transmitter allows the user to control bidirectional synchronous serial communications in master mode. In synchronous mode, the following bits must be kept cleared: ● LINEN bit in the UART_CR3 register ●...

  • Page 327: Figure 121. Uart Example Of Synchronous Transmission

    RM0016 Universal asynchronous receiver transmitter (UART) Figure 121. UART example of synchronous transmission Data out Data in Synchronous device UART (for example slave SPI) SCLK Clock Figure 122. UART data clock timing diagram (M=0) Idle or next Idle or preceding Start Stop transmission...

  • Page 328: Single Wire Half Duplex Communication

    Universal asynchronous receiver transmitter (UART) RM0016 Figure 124. RX data setup/hold time SCLK (capture strobe on SCLK rising edge in this example) Data on RX valid DATA bit (from slave) SETUP HOLD 1/16 bit time = 1/16*f SCLK SETUP HOLD Note: The function of UART_CK is different in Smartcard mode.

  • Page 329: Figure 125. Iso 7816-3 Asynchronous Protocol

    RM0016 Universal asynchronous receiver transmitter (UART) Figure 125. ISO 7816-3 asynchronous protocol Guard time Start Line pulled low by receiver during stop in case of parity error When connected to a smartcard, the UART_TX output drives a bidirectional line that is also driven by the smartcard.

  • Page 330: Irda Sir Endec Block

    Universal asynchronous receiver transmitter (UART) RM0016 ● The output enable signal for the Smartcard I/O enables driving into a bidirectional line which is also driven by the Smartcard. This signal is active while transmitting the start and data bits and transmitting NACK. While transmitting the stop bits this signal is disabled, so that the UART weakly drives a ‘1’...
  • Page 331 RM0016 Universal asynchronous receiver transmitter (UART) The SIR receive decoder demodulates the return-to-zero bit stream from the infrared detector and outputs the received NRZ serial bit stream to UART. The decoder input is normally HIGH (marking state) in the idle state. The transmit encoder output has the opposite polarity to the decoder input.

  • Page 332: Figure 127. Irda Sir Endec- Block Diagram

    Universal asynchronous receiver transmitter (UART) RM0016 Figure 127. IrDA SIR ENDEC- block diagram IREN bit UART_TX pin IrDA IrDA_TX Transmit Encoder IREN bit UART IrDA IrDA_RX UART_RX pin Receive Decoder Figure 128. IrDA data modulation (3/16) - normal mode stop bit Start bit period IrDA_TDO...

  • Page 333: Lin Mode Functional Description

    RM0016 Universal asynchronous receiver transmitter (UART) 22.4 LIN mode functional description In LIN mode, 8-bit data format with 1 stop bit is required in accordance with the LIN standard. To configure these settings, clear the M bit in UART_CR1 register and clear the STOP[1:0] bits in the UART_CR3 register.
  • Page 334 Universal asynchronous receiver transmitter (UART) RM0016 LIN break and delimiter detection The UART features a break detection circuit which is totally independent from the normal UART receiver. A break can be detected whenever it occurs, during idle state or during a frame.

  • Page 335: Figure 129. Break Detection In Lin Mode (11-Bit Break Length - Lbdl Bit Is Set)

    RM0016 Universal asynchronous receiver transmitter (UART) Figure 129. Break detection in LIN mode (11-bit break length - LBDL bit is set) Case 1: break signal not long enough => break discarded, LBDF is not set “Short” Break Frame RX line Capture Strobe Break State machine Idle...

  • Page 336: Figure 130. Break Detection In Lin Mode Vs Framing Error Detection

    Universal asynchronous receiver transmitter (UART) RM0016 Figure 130. Break detection in LIN mode vs framing error detection In these examples, we suppose that LBDL=1 (11-bit break length), M=0 (8-bit data) Case 1: break occurring after an Idle RX line data 1 IDLE BREAK data2 (0x55)

  • Page 337: Slave Mode With Automatic Resynchronization Disabled

    RM0016 Universal asynchronous receiver transmitter (UART) 22.4.2 Slave mode with automatic resynchronization disabled Note: This feature is only available in UART2 and UART3. UART initialization Procedure: Select the desired baudrate by programming UART_BRR2 and UART_BRR1 registers, Enable transmitter and receiver by setting TEN and REN bits in UART_CR2 register, Enable LSLV bit in UART_CR6 register, Enable LIN mode by setting LINEN bit in UART_CR3 register, LIN Header reception...

  • Page 338: Figure 131. Lin Identifier Field Parity Bits

    Universal asynchronous receiver transmitter (UART) RM0016 Discard response Software can set the RWU bit immediately. LIN Slave parity In LIN Slave mode (LINEN and LSLV bits are set) LIN parity checking can be enabled by setting the PCEN bit. An interrupt is generated if an ID parity error occurs (PE bit rises) and the PIEN bit is set.

  • Page 339: Figure 133. Lin Header Reception Time-Out

    RM0016 Universal asynchronous receiver transmitter (UART) LHE is set if one of the following conditions occurs: ● Break Delimiter is too short ● Synch Field is different from 55h ● Framing error in Synch Field or Identifier Field ● A LIN header reception time-out Note: If a LIN header error occurs, the LSF bit in the UART_CR6 register must be cleared by software...

  • Page 340: Slave Mode With Automatic Resynchronization Enabled

    Universal asynchronous receiver transmitter (UART) RM0016 When checking this time-out, the slave node is desynchronized for the reception of the LIN Break and Synch fields. Consequently, a margin must be allowed, taking into account the worst case: This occurs when the LIN identifier lasts exactly 10 TBIT_MASTER periods. In this case, the LIN Break and Synch fields last 49 - 10 = 39 TBIT_MASTER periods.

  • Page 341: Figure 134. Lin Synch Field Measurement

    RM0016 Universal asynchronous receiver transmitter (UART) Figure 134. LIN synch field measurement = Master clock period MASTER = UARTDIV.T = Baud Rate period MASTER SM = Synch Measurement Register (19 bits) LIN Synch Field LIN Break Next Start Start Break Stop Bit0 Bit1 Bit2...

  • Page 342: Figure 136. Uartdiv Read / Write Operations When Ldum = 1

    Universal asynchronous receiver transmitter (UART) RM0016 Figure 136. UARTDIV read / write operations when LDUM = 1 Write UART2_BRR2 Write UART2_BRR1 LIN Sync Field UARTDIV[11:4] UARTDIV[15:12] UARTDIV_NOM Measurement UARTDIV[3:0] RXNE=1 UARTDIV[11:4] UARTDIV[15:12] UARTDIV_MEAS UARTDIV[3:0] Update at end of LDUM is reset Synch Field UARTDIV[11:4] UARTDIV[15:12] UARTDIV...
  • Page 343 RM0016 Universal asynchronous receiver transmitter (UART) Note: Deviation checking is based on the current baudrate and not on the nominal one. Therefore, in order to guarantee correct deviation checking, the baudrate generator must reload the nominal value before each new Break reception. This nominal value is programmed by the application during initialization.
  • Page 344 Universal asynchronous receiver transmitter (UART) RM0016 UART clock tolerance when unsynchronized When LIN slaves are unsynchronized (meaning no characters have been transmitted for a relatively long time), the maximum tolerated deviation of the UART clock is +/-14%. If the deviation is within this range then the LIN Break is detected properly when a new reception occurs.

  • Page 345: Lin Mode Selection

    RM0016 Universal asynchronous receiver transmitter (UART) Impact of clock deviation on maximum baud rate The choice of the nominal baud rate (UARTDIVNOM) will influence both the quantization error (DQUANT) and the measurement error (DMEAS). The worst case occurs for UARTDIVMIN. Consequently, at a given CPU frequency, the maximum possible nominal baud rate (LPRMIN) should be chosen with respect to the maximum tolerated deviation given by the equation:...

  • Page 346: Uart Low Power Modes

    Universal asynchronous receiver transmitter (UART) RM0016 22.5 UART low power modes Table 59. UART interface behavior in low power modes Mode Description No effect on UART. Wait UART interrupts cause the device to exit from Wait mode. UART registers are frozen. Halt In Halt mode, the UART stops transmitting/receiving until Halt mode is exited.

  • Page 347: Figure 138. Uart Interrupt Mapping Diagram

    RM0016 Universal asynchronous receiver transmitter (UART) Figure 138. UART interrupt mapping diagram TCIEN Transmitter Interrupt TIEN IDLE ILIEN RIEN OR/LHE RIEN Receiver Interrupt RXNE PIEN LBDF LBDIEN LHDF LHDIEN Doc ID 14587 Rev 8 347/449...

  • Page 348: Uart Registers

    Universal asynchronous receiver transmitter (UART) RM0016 22.7 UART registers 22.7.1 Status register (UART_SR) Address offset: 0x00 Reset value: 0xC0 RXNE IDLE OR/LHE rc_w0 rc_w0 Bit 7 TXE: Transmit data register empty This bit is set by hardware when the content of the TDR register has been transferred into the shift register.
  • Page 349 RM0016 Universal asynchronous receiver transmitter (UART) Bit 3 OR: Overrun error This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RXNE=1. An interrupt is generated if RIEN=1 in the UART_CR2 register.

  • Page 350: Data Register (Uart_Dr)

    Universal asynchronous receiver transmitter (UART) RM0016 22.7.2 Data register (UART_DR) Address offset: 0x01 Reset value: 0xXX DR[7:0] Bits 7:0 DR[7:0]: Data value Contains the Received or Transmitted data character, depending on whether it is read from or written to. The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR) The TDR register provides the parallel interface between the internal bus and the output shift register.

  • Page 351: Baud Rate Register 2 (Uart_Brr2)

    RM0016 Universal asynchronous receiver transmitter (UART) 22.7.4 Baud rate register 2 (UART_BRR2) Address offset: 0x03 Reset value: 0x00 UART_DIV[15:12] UART_DIV[3:0] Bits 7:4 UART_DIV[15:12] MSB of UART_DIV. These 4 bits define the MSB of the UART Divider (UART_DIV) Bits 3:0 UART_DIV[3:0]: LSB of UART_DIV. These 4 bits define the LSB of the UART Divider (UART_DIV) 22.7.5 Control register 1 (UART_CR1)

  • Page 352: Control Register 2 (Uart_Cr2)

    Universal asynchronous receiver transmitter (UART) RM0016 Bit 2 PCEN: Parity control enable. – UART Mode This bit selects the hardware parity control (generation and detection). When the parity control is enabled, the computed parity is inserted at the MSB position (9th bit if M=1; 8th bit if M=0) and parity is checked on the received data.
  • Page 353 RM0016 Universal asynchronous receiver transmitter (UART) (1) (2) Bit 3 TEN: Transmitter enable This bit enables the transmitter. It is set and cleared by software. 0: Transmitter is disabled 1: Transmitter is enabled Bit 2 REN: Receiver enable This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled 1: Receiver is enabled and begins searching for a start bit Bit 1 RWU: Receiver wakeup...

  • Page 354: Control Register 3 (Uart_Cr3)

    Universal asynchronous receiver transmitter (UART) RM0016 22.7.7 Control register 3 (UART_CR3) Address offset: 0x06 Reset value: 0x00 LINEN STOP[1:0] CLKEN CPOL CPHA LBCL Reserved Bit 7 Reserved, must be kept cleared. Bit 6 LINEN: LIN mode enable This bit is set and cleared by software. 0: LIN mode disabled 1: LIN mode enabled Bits 5:4 STOP: STOP bits.

  • Page 355: Control Register 4 (Uart_Cr4)

    RM0016 Universal asynchronous receiver transmitter (UART) 22.7.8 Control register 4 (UART_CR4) Address offset: 0x07 Reset value: 0x00 LBDIEN LBDL LBDF ADD[3:0] Reserved Bit 7 Reserved, must be kept cleared. Bit 6 LBDIEN: LIN Break Detection Interrupt Enable. Break interrupt mask (break detection using break delimiter). 0: LIN break detection interrupt disabled 1: LIN break detection interrupt enabled Bit 5 LBDL: LIN Break Detection Length.

  • Page 356: Control Register 5 (Uart_Cr5)

    Universal asynchronous receiver transmitter (UART) RM0016 22.7.9 Control register 5 (UART_CR5) Address offset: 0x08 Reset value: 0x00 SCEN NACK HDSEL IRLP IREN Reserved Reserved Bits 7:6 Reserved, must be kept cleared. Bit 5 SCEN: Smartcard mode enable. This bit is used for enabling Smartcard mode. 0: Smartcard Mode disabled 1: Smartcard Mode enabled Note: This bit is not available for UART3.

  • Page 357: Control Register 6 (Uart_Cr6)

    RM0016 Universal asynchronous receiver transmitter (UART) 22.7.10 Control register 6 (UART_CR6) Address offset: 0x09 Reset value: 0x00 LDUM LSLV LASE LHDIEN LHDF Reserved Reserved rc_w0 rc_w0 Note: This register is not available for UART1. Bit 7 LDUM: LIN Divider Update Method 0: LDIV is updated as soon as BRR1 is written (if no automatic resynchronization update occurs at the same time).

  • Page 358: Guard Time Register (Uart_Gtr)

    Universal asynchronous receiver transmitter (UART) RM0016 22.7.11 Guard time register (UART_GTR) Address offset: 0x09 (UART1), 0x0A (UART2) Reset value: 0x00 GT[7:0] Bits 7:0 GT[7:0]: Guard time value. This register gives the Guard time value in terms of number of baud clocks. This is used in Smartcard mode.The Transmission Complete flag is set after this guard time value.

  • Page 359: Prescaler Register (Uart_Pscr)

    RM0016 Universal asynchronous receiver transmitter (UART) 22.7.12 Prescaler register (UART_PSCR) Address offset: 0x0A (UART1), 0x0B (UART2) Reset value: 0x00 Note: Care must be taken to program this register with correct value, when both Smartcard and IrDA interfaces are used in the application PSC[7:0] Bits 7:0 PSC[7:0]: Prescaler value.

  • Page 360: Uart Register Map And Reset Values

    Universal asynchronous receiver transmitter (UART) RM0016 22.7.13 UART register map and reset values Table 61. UART1 register map Register Address name RXNE UART1_SR IDLE 0x00 Reset Value UART1_DR 0x01 Reset Value UART_DIV[11:4] UART1_BRR1 0x02 00000000 Reset Value UART_DIV[15:12] UART_DIV[3:0] UART1_BRR2 0x03 0000 0000...

  • Page 361: Table 63. Uart3 Register Map

    RM0016 Universal asynchronous receiver transmitter (UART) Table 62. UART2 register map (continued) Register Address name UART2_CR4 LBDIEN LBDL LBDF ADD[3:0] 0x07 Reset Value 0000 SCEN NACK HDSEL IRLP IREN UART2_CR5 0x08 Reset Value UART2_CR6 LDUM LSLV LASE LHDIEN LHDF 0x09 Reset Value UART2_GTR 0x0A...

  • Page 362: Controller Area Network (Becan)

    Controller area network (beCAN) RM0016 Controller area network (beCAN) 23.1 Introduction The Basic Enhanced CAN peripheral, named beCAN, interfaces the CAN network. It supports the CAN protocol version 2.0A and B. It has been designed to manage high number of incoming messages efficiently with a minimum CPU load. It also meets the priority requirements for transmit messages.

  • Page 363: Becan General Description

    RM0016 Controller area network (beCAN) 23.3 beCAN general description In today’s CAN applications, the number of nodes in a network is increasing and often several networks are linked together via gateways. Typically the number of messages in the system (and thus to be handled by each node) has significantly increased. In addition to the application messages, Network Management and Diagnostic messages have been introduced.

  • Page 364: Tx Mailboxes

    Controller area network (beCAN) RM0016 23.3.3 Tx mailboxes Three transmit mailboxes are provided to the software for setting up messages. The Transmission Scheduler decides which mailbox has to be transmitted first. 23.3.4 Acceptance filters The beCAN provides six scalable/configurable identifier filter banks for selecting the incoming messages the software needs and discarding the others.

  • Page 365: Operating Modes

    RM0016 Controller area network (beCAN) Figure 141. beCAN operating modes Reset Sleep SLAK = 1 INAK = 0 Normal Initialization INRQ . ACK SLAK = 0 SLAK = 0 INAK = 1 INAK = 0 INRQ . SYNC . SLEEP 23.4 Operating modes beCAN has three main operating modes: Initialization, Normal and Sleep.

  • Page 366: Normal Mode

    Controller area network (beCAN) RM0016 23.4.2 Normal mode Once the initialization has been done, the software must request the hardware to enter Normal mode, to synchronize on the CAN bus and start reception and transmission. This request to enter Normal mode is done by clearing the INRQ bit in the CAN_MCR register. Afterwards, the beCAN is synchronized with the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits (Bus Idle state) before finishing the switch to Normal mode and being ready to take part in bus activities.

  • Page 367: Test Modes

    RM0016 Controller area network (beCAN) 23.5 Test modes Test modes can be selected by the SILM and LBKM bits in the CAN_DGR register. These bits must be configured while beCAN is in Initialization mode. Once a test mode has been selected, the INRQ bit in the CAN_MCR register must be reset to enter Normal mode.

  • Page 368: Loop Back Combined With Silent Mode

    Controller area network (beCAN) RM0016 Note: As the Tx line is still active in this mode, be aware that it can disturb the communication on the CAN bus. 23.5.3 Loop back combined with silent mode It is also possible to combine Loop Back mode and Silent mode by setting the LBKM and SILM bits in the CAN_DGR register.
  • Page 369 RM0016 Controller area network (beCAN) By transmit request order: The transmit mailboxes can be configured as a transmit FIFO by setting the TXFP bit in the CAN_MCR register. In this mode the priority order is given by the transmit request order. This mode is very useful for segmented transmission.

  • Page 370: Figure 145. Transmit Mailbox States

    Controller area network (beCAN) RM0016 Figure 145. Transmit mailbox states EMPTY RQCP = X TXOK = X TXRQ = 1 TME = 1 PENDING RQCP = 0 Mailbox has TXOK = 0 highest priority TME = 0 ABRQ = 1 Mailbox does not have highest priority EMPTY...

  • Page 371: Reception Handling

    RM0016 Controller area network (beCAN) 23.6.2 Reception handling For the reception of CAN messages, three mailboxes organized as a FIFO are provided. In order to save CPU load, simplify the software and guarantee data consistency, the FIFO is managed completely by hardware. The application accesses the messages stored in the FIFO through the FIFO output mailbox.

  • Page 372: Identifier Filtering

    Controller area network (beCAN) RM0016 If the application does not release the mailbox, the next valid message will be stored in the FIFO which enters pending_2 state (FMP[1:0] = 0b10). The storage process is repeated for the next valid message putting the FIFO into pending_3 state (FMP[1:0] = 0b11). At this point, the software must release the output mailbox by setting the RFOM bit, so that a mailbox is free to store the next valid message.
  • Page 373 RM0016 Controller area network (beCAN) Scalable width To optimize and adapt the filters to the application needs, each filter bank can be scaled independently. Depending on the filter scale a filter bank provides: – One 32-bit filter for the STDID[10:0] / EXID[28:18], IDE, EXID[17:0] and RTR bits. –...

  • Page 374: Figure 147. 32-Bit Filter Bank Configuration (Fscx Bits = 0B11 In Can_Fcrx Register)

    Controller area network (beCAN) RM0016 Note: In 32-bit configuration, the FMLx and FMHx bits must have the same value to ensure that the four Mask/Identifier registers are in the same mode. When a standard identifier is received (IDE bit is zero), the extended part of 32-bit or 16-bit filters is not compared.

  • Page 375: Figure 149. 16/8-Bit Filter Bank Configuration (Fscx Bits = 0B01 In Can_Fcrx Register)

    RM0016 Controller area network (beCAN) Figure 149. 16/8-bit filter bank configuration (FSCx bits = 0b01 in CAN_FCRx register) Filter registers Filter mode STID [2:0] STID[10:3] / EXID FMHx = 0 FMHx = 0 FMHx = 1 FMHx = 1 Mapping / EXID EXID[28:21] [17:15]...

  • Page 376: Table 64. Example Of Filter Numbering

    Controller area network (beCAN) RM0016 Filter match index Once a message has been received in the FIFO it is available to the application. Typically application data are copied into RAM locations. To copy the data to the right location the application has to identify the data by means of the identifier.

  • Page 377: Figure 151. Filter Banks Configured As In The Example In

    RM0016 Controller area network (beCAN) Filter priority rules Depending on the filter combination it may occur that an identifier passes successfully through several filters. In this case the filter match value stored in the receive mailbox is chosen according to the following rules: –...

  • Page 378: Message Storage

    Controller area network (beCAN) RM0016 23.6.4 Message storage The interface between the software and the hardware for the CAN messages is implemented by means of mailboxes. A mailbox contains all information related to a message; identifier, data, control, status and time stamp information. Transmit mailbox The software sets up the message to be transmitted in an empty transmit mailbox.

  • Page 379: Table 66. Receive Mailbox Mapping

    RM0016 Controller area network (beCAN) Receive mailbox When a message has been received, it is available to the software in the FIFO output mailbox. Once the software has handled the message (e.g. read it) the software must release the FIFO output mailbox by means of the RFOM bit in the CAN_RFR register to make the next incoming message available.

  • Page 380: Error Management

    Controller area network (beCAN) RM0016 23.6.5 Error management The error management as described in the CAN protocol is handled entirely by hardware using a Transmit Error Counter (CAN_TECR register) and a Receive Error Counter (CAN_RECR register), which get incremented or decremented according to the error condition.

  • Page 381: Bit Timing

    RM0016 Controller area network (beCAN) 23.6.6 Bit timing The bit timing logic monitors the serial bus-line and performs sampling and adjustment of the sample point by synchronizing on the start-bit edge and resynchronizing on the following edges. Its operation may be explained simply by splitting nominal bit time into three segments as follows: –...

  • Page 382: Figure 154. Can Frames

    Controller area network (beCAN) RM0016 Figure 154. CAN frames Inter-Frame Space Inter-Frame Space Data Frame (Standard identifier) or Overload Frame 44 + 8 * N Ctrl Field Data Field CRC Field Ack Field Arbitration Field 8 * N STID[10:0] Inter-Frame Space Inter-Frame Space Data Frame (Extended identifier) or Overload Frame...

  • Page 383: Interrupts

    RM0016 Controller area network (beCAN) SOF = Start Of Frame; ID = Identifier; RTR = Remote Transmission Request; IDE = Identifier Extension; r0, r1 = Reserved bits; DLC = Data Length Code; CRC = Cyclic Redundancy Code; Error flag: 6 dominant bits if node is error active else 6 recessive bits. Suspend transmission: applies to error passive nodes only.

  • Page 384: Register Access Protection

    Controller area network (beCAN) RM0016 23.8 Register access protection Erroneous access to certain configuration registers can cause the hardware to temporarily disturb the whole CAN network. Therefore the following registers can be modified by software only while the hardware is in initialization mode: CAN_BTR1, CAN_BTR2, CAN_FCR1, CAN_FCR2, CAN_FMR1, CAN_FMR2 and CAN_DGR registers.

  • Page 385: Becan Registers

    RM0016 Controller area network (beCAN) 23.11 beCAN registers 23.11.1 CAN master control register (CAN_MCR) Address offset: 0x00 Reset value: 0x02 TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ Bit 7 TTCM Time Triggered Communication Mode 0: Time Triggered Communication mode disabled. 1: Time Triggered Communication mode enabled Note: For more information on Time Triggered Communication mode, please refer to Section 23.4.4:...

  • Page 386: Can Master Status Register (Can_Msr)

    Controller area network (beCAN) RM0016 Bit 1 SLEEP Sleep Mode Request This bit must be set by software to request the CAN hardware to enter Sleep mode. If the AWUM bit is not set, the Sleep mode is entered as soon as the current CAN activity (CAN frame transmission or reception) has completed.

  • Page 387: Can Transmit Status Register (Can_Tsr)

    RM0016 Controller area network (beCAN) Bit 1 SLAK Sleep Acknowledge This bit is set by hardware and indicates to the software that the CAN hardware is now in sleep mode. This bit acknowledges the sleep mode request from the software (set SLEEP bit in CAN_MCR register).

  • Page 388: Can Transmit Priority Register (Can_Tpr)

    Controller area network (beCAN) RM0016 Bit 1 RQCP1 Request Completed for Mailbox 1 This bit is set by hardware to signal that the last request for mailbox 1 has been completed. The request could be a transmit or an abort request. This bit is cleared by software writing 1.

  • Page 389: Can Receive Fifo Register (Can_Rfr)

    RM0016 Controller area network (beCAN) 23.11.5 CAN receive FIFO register (CAN_RFR) Address offset: 0x04 Reset value: 0x00 RFOM FOVR FULL FMP[1:0] Reserved Reserved rc_w1 rc_w1 Bit 7:6 Reserved. Bit 5 RFOM Release FIFO Output Mailbox Set by software to release the output mailbox of the FIFO. The output mailbox can only be released when at least one message is pending in the FIFO.

  • Page 390: Can Interrupt Enable Register (Can_Ier)

    Controller area network (beCAN) RM0016 23.11.6 CAN interrupt enable register (CAN_IER) Address offset: 0x05 Reset value: 0x00 WKUIE FOVIE FFIE FMPIE TMEIE Reserved Bit 7 WKUIE Wakeup Interrupt Enable 0: No interrupt when WKUI is set. 1: Interrupt generated when WKUI bit is set. Bit 6:4 Reserved.

  • Page 391: Can Diagnostic Register (Can_Dgr)

    RM0016 Controller area network (beCAN) 23.11.7 CAN diagnostic register (CAN_DGR) Address offset: 0x06 Reset value: 0x0C TXM2E SAMP SILM LBKM Reserved Bit 7:5 Reserved. Bit 4 TXM2E TX Mailbox 2 enable 0: Force compatibility with ST7 beCAN (2 TX Mailboxes) - reset value 1: Enables the third TX Mailbox (Mailbox number 2) Bit 3 RX CAN Rx Signal Monitors the actual value of the CAN_RX Pin.

  • Page 392: Can Error Status Register (Can_Esr)

    Controller area network (beCAN) RM0016 23.11.9 CAN error status register (CAN_ESR) Address offset: See Table 70. Reset value: 0000 0000 (00h) LEC[2:0] BOFF EPVF EWGF Reserved Reserved Bit 7 Reserved. Bit 6:4 LEC[2:0] Last error code This field holds a code which indicates the type of the last error detected on the CAN bus. If a message has been transferred (reception or transmission) without error, this field will be cleared to ‘0’.

  • Page 393: Can Error Interrupt Enable Register (Can_Eier)

    RM0016 Controller area network (beCAN) 23.11.10 CAN error interrupt enable register (CAN_EIER) Address offset: See Table 70. Reset value: 0000 0000 (00h) ERRIE LECIE BOFIE EPVIE EWGIE Reserved Reserved Bit 7 ERRIE Error interrupt enable 0: No interrupt is generated when an error condition is pending in the CAN_ESR (ERRI bit in CAN_MSR is set).

  • Page 394: Can Receive Error Counter Register (Can_Recr)

    Controller area network (beCAN) RM0016 23.11.12 CAN receive error counter register (CAN_RECR) Address offset: See Table 70. Reset value: 0000 0000 (00h) REC[7:0] Bits 7:0 REC[7:0] Receive error counter This is the Receive Error Counter implementing part of the fault confinement mechanism of the CAN protocol.

  • Page 395: Can Bit Timing Register 2 (Can_Btr2)

    RM0016 Controller area network (beCAN) 23.11.14 CAN bit timing register 2 (CAN_BTR2) Address offset: See Table 70. Reset value: 0x23 BS2[2:0] BS1[3:0] Reserved This register can only be accessed by the software when the CAN hardware is in initialization mode. Bit 7 Reserved, must be kept cleared.

  • Page 396: 23.11.15 Mailbox Registers

    Controller area network (beCAN) RM0016 23.11.15 Mailbox registers This chapter describes the registers of the transmit and receive mailboxes. Refer to Section 23.6.4: Message storage for detailed register mapping. Transmit and receive mailboxes have the same registers except: – CAN_MCSR register in a transmit mailbox is replaced by CAN_MFMIR register in a receive mailbox.
  • Page 397 RM0016 Controller area network (beCAN) Bit 1 ABRQ Abort request for mailbox Set by software to abort the transmission request for the corresponding mailbox. Cleared by hardware when the mailbox becomes empty. Setting this bit has no effect when the mailbox is not pending for transmission. Bit 0 TXRQ Transmit mailbox request Set by software to request the transmission for the corresponding mailbox.
  • Page 398 Controller area network (beCAN) RM0016 CAN mailbox identifier register 1 (CAN_MIDR1) Address offset: See Table 65. Table 66. Reset value: 0xXX STID[10:6] / EXID[28:24] Reserved Bit 7 Reserved. Bit 6 IDE Extended identifier This bit defines the identifier type of message in the mailbox. 0: Standard identifier.
  • Page 399 RM0016 Controller area network (beCAN) CAN mailbox identifier register 3 (CAN_MIDR3) Address offset: See Table 65. Table 66. Reset value: 0xXX EXID[15:8] Bits 7:0 EXID[15:8] Extended identifier Bit 15 to 8 of the “Extended” part of the extended identifier. CAN mailbox identifier register 4 (CAN_MIDR4) Address offset: See Table 65.
  • Page 400 Controller area network (beCAN) RM0016 CAN mailbox data register x (CAN_MDAR) (x= 1 .. 8) Address offset: See Table 65. Table 66. Reset value: 0xXX DATA[7:0] Bits 7:0 DATA[7:0] Data A data byte of the message. A message can contain from 0 to 8 data bytes. Note: These bits are write protected when the mailbox is not in empty state.

  • Page 401: 23.11.16 Can Filter Registers

    RM0016 Controller area network (beCAN) 23.11.16 CAN filter registers CAN filter mode register 1 (CAN_FMR1) Address offset: See Table 70. Reset value: 0x00 FMH3 FML3 FMH2 FML2 FMH1 FML1 FMH0 FML0 Bit 7 FMH3 Filter 3 mode high Mode of the high identifier/mask registers of Filter 3. 0: High registers are in mask mode 1: High registers are in identifier list mode Bit 6 FML3 Filter 3 mode low...
  • Page 402 Controller area network (beCAN) RM0016 CAN filter mode register 2 (CAN_FMR2) Address offset: See Table 70. Reset value: 0x00 FMH5 FML5 FMH4 FML4 Reserved Bits 7:4 Reserved. Bit 3 FMH5 Filter 5 mode high Mode of the high identifier/mask registers of Filter 5. 0: High registers are in mask mode 1: High registers are in identifier list mode Bits 2 FML5 Filter 5 mode low...
  • Page 403 RM0016 Controller area network (beCAN) CAN filter configuration register 1 (CAN_FCR1) Address offset: See Table 70. Reset value: 0x00 FSC11 FSC10 FACT1 FSC01 FSC00 FACT0 Reserved Reserved Bit 7 Reserved. Bits 6:5 FSC1[1:0] Filter scale configuration These bits define the scale configuration of Filter 1. Bit 4 FACT1 Filter Active The software sets this bit to activate Filter 1.
  • Page 404 Controller area network (beCAN) RM0016 CAN filter configuration register 2 (CAN_FCR2) Address offset: See Table 70. Reset value: 0x00 FSC31 FSC30 FACT3 FSC21 FSC20 FACT2 Reserved Reserved Bit 7 Reserved. Bits 6:5 FSC3[1:0] Filter scale configuration These bits define the scale configuration of Filter 3. Bit 4 FACT3 Filter active The software sets this bit to activate Filter 3.
  • Page 405 RM0016 Controller area network (beCAN) CAN filter configuration register 3 (CAN_FCR3) Address offset: See Table 70. Reset value: 0x00 FSC51 FSC50 FACT5 FSC41 FSC40 FACT4 Reserved Reserved Bit 7 Reserved. Bits 6:5 FSC5[1:0] Filter scale configuration These bits define the scale configuration of Filter 5. Bit 4 FACT5 Filter active The software sets this bit to activate Filter 5.
  • Page 406 Controller area network (beCAN) RM0016 CAN filter bank i register x (CAN_FiRx) (i = 0 .. 5, x = 1 .. 8) Address offset: See Figure 157. Reset value: 0xXX FB(7:0] Bits 7:0 FB[7:0]: Filter bits – Identifier Each bit of the register specifies the level of the corresponding bit of the expected identifier. 0: Dominant bit is expected 1: Recessive bit is expected –...

  • Page 407: Can Register Map

    RM0016 Controller area network (beCAN) 23.12 CAN register map Figure 156. CAN register mapping 0x00 CAN MASTER CONTROL REGISTER CAN_MCR 0x01 CAN_MSR CAN MASTER STATUS REGISTER 0x02 CAN TRANSMIT STATUS REGISTER CAN_TSR 0x03 CAN TRANSMIT PRIORITY REGISTER CAN_TPR 0x04 CAN RECEIVE FIFO REGISTER CAN_RFR 0x05 CAN_IER...

  • Page 408: Page Mapping For Can

    Controller area network (beCAN) RM0016 23.12.1 Page mapping for CAN Figure 157. CAN page mapping PAGE 0 PAGE 1 PAGE 2 PAGE 3 PAGE 4 0x00 CAN_F2R1 CAN_F4R1 CAN_F0R1 CAN_MCSR CAN_MCSR 0x01 CAN_F2R2 CAN_F4R2 CAN_F0R2 CAN_MDLCR CAN_MDLCR 0x02 CAN_F2R3 CAN_F4R3 CAN_MIDR1 CAN_F0R3 CAN_MIDR1...

  • Page 409: Table 68. Becan Control And Status Page - Register Map And Reset Values

    RM0016 Controller area network (beCAN) Table 68. beCAN control and status page - register map and reset values Address Register name Offset CAN_MCR TTCM ABOM AWUM NART RFLM TXFP SLEEP INRQ 0x00 Reset Value CAN_MSR WKUI ERRI SLAK INAK 0x01 Reset Value CAN_TSR TXOK2...

  • Page 410: Table 70. Becan Filter Configuration Page - Register Map And Reset Values

    Controller area network (beCAN) RM0016 Table 69. beCAN mailbox pages - register map and reset values (continued) Address Register name Offset CAN_MTSRL TIME7 TIME6 TIME5 TIME4 TIME3 TIME2 TIME1 TIME0 0x0E Reset Value CAN_MTSRH TIME15 TIME14 TIME13 TIME12 TIME11 TIME10 TIME9 TIME8 0x0F...

  • Page 411: Analog/Digital Converter (Adc)

    RM0016 Analog/digital converter (ADC) Analog/digital converter (ADC) 24.1 Introduction ADC1 and ADC2 are 10-bit successive approximation Analog to Digital Converters. They have up to 16 multiplexed input channels (the exact number of channels is indicated in the datasheet pin description). A/D Conversion of the various channels can be performed in single, and continuous modes.

  • Page 412: Figure 158. Adc1 Block Diagram

    Analog/digital converter (ADC) RM0016 Figure 158. ADC1 block diagram Analog Watchdog Event EOCIE AWDIE End of Conversion Flags Masks ADC Interrupt to ITC ANALOG AWEN Enable bits (10 channels) AWS status bits (10 channels) WATCHDOG High Threshold (10-bits) Low Threshold (10-bits) DATA BUFFER (10 x 10 bits) or (8 x 10 bits) DATA REGISTER...

  • Page 413: Figure 159. Adc2 Block Diagram

    RM0016 Analog/digital converter (ADC) Figure 159. ADC2 block diagram 80/64-pin REF+ devices only REF- EOC Interrupt to CPU DATA REGISTER (1 x 10-bits) ANALOG AIN0 ANALOG TO DIGITAL Prescaler MASTER AIN1 CONVERTER /2, /3, /4, ../18 AIN15 GPIO Ports CH[2:0] Channel select ADC_ETR CONT Single/Continuous ADON Power on /Start conversion...

  • Page 414: Adc Pins

    Analog/digital converter (ADC) RM0016 24.4 ADC pins Table 71. ADC pins Name Signal type Remarks Input, Analog Analog power supply. This input is bonded to V supply devices that have no external V pin. Input, Analog Ground for analog power supply. This input is bonded to supply ground in devices that have no external V pin.

  • Page 415: Channel Selection

    RM0016 Analog/digital converter (ADC) 24.5.3 Channel selection There are up to 16 external input channels that can be selected through CH[0:3] bits of the ADC_SR register. The number of external channels depends on the device (refer to the product datasheets). If the channel selection is changed during a conversion, the current conversion is reset and a new start pulse is sent to the ADC.

  • Page 416: Overrun Flag

    Analog/digital converter (ADC) RM0016 Note: When using scan mode, it is not possible to use channels AIN0 to AINn in output mode because the output stage of each channel is disabled when it is selected by the ADC multiplexer. A single conversion is performed for each channel starting with AIN0 and the data is stored in the data buffer registers ADC_DBxR.

  • Page 417: Analog Watchdog

    RM0016 Analog/digital converter (ADC) 24.5.6 Analog watchdog The analog watchdog is enabled for single conversion and non-buffered continuous conversion modes by setting the AWDEN bit in the ADC_CSR register. The AWD analog watchdog flag is set if the analog voltage converted by the ADC is below a low threshold or above a high threshold as shown in Figure 160.

  • Page 418: Conversion On External Trigger

    Analog/digital converter (ADC) RM0016 24.5.7 Conversion on external trigger Conversion can be triggered by an rising edge event on the ADC_ETR pin or a TRGO event from a timer. Refer to the datasheet for details on the timer trigger, as this is product depend- ent).

  • Page 419: Figure 161. Timing Diagram In Single Mode (Cont = 0)

    RM0016 Analog/digital converter (ADC) Figure 161. Timing diagram in single mode (CONT = 0) fADC Software sets ADON bit 1st time Software sets ADON bit 2nd time ADON ADC Conversion Conversion Time (tCONV) tSTAB Software resets EOC bit Figure 162. Timing diagram in continuous mode (CONT = 1) fADC Software sets ADON bit 1st time Software resets ADON or CONT bit...

  • Page 420: Adc Low Power Modes

    Analog/digital converter (ADC) RM0016 24.6 ADC low power modes Table 72. Low power modes Mode Description Wait No effect on ADC In devices with extended features, the ADC is automatically switched off Halt/ before entering Halt/Active-halt mode. After waking up from Active-halt, the Active-halt ADON bit must be set by software to power on the ADC, and a delay of 7 µs is needed before starting a new conversion.

  • Page 421: Table 74. Adc Interrupts In Buffered Continuous Mode (Adc1)

    RM0016 Analog/digital converter (ADC) Table 74. ADC interrupts in buffered continuous mode (ADC1) Enable bits Status flags Exit Exit from from AWSx Wait Halt Don’t The flag is set at the end care of BSIZE conversions The flag is set at the end Don’t of BSIZE conversions care...

  • Page 422: Table 75. Adc Interrupts In Scan Mode (Adc1)

    Analog/digital converter (ADC) RM0016 Table 75. ADC interrupts in scan mode (ADC1) Control bits Status bits Exit Exit from from AWSx Wait Halt Don’t The flag is set at the end care of the scan sequence The flag is set at the end Don’t of the scan sequence care...

  • Page 423: Data Alignment

    RM0016 Analog/digital converter (ADC) 24.8 Data alignment ALIGN bit in the ADC_CR2 register selects the alignment of data stored after conversion. Data can be aligned in the following ways. Right Alignment: 8 Least Significant bits are written in the ADC_DL register, then the remaining Most Significant bits are written in the ADC_DH register.

  • Page 424: Schmitt Trigger Disable Registers

    Analog/digital converter (ADC) RM0016 24.10 Schmitt trigger disable registers The ADC_TDRH and ADC_TDRL registers are used to disable the Schmitt triggers available in the AIN analog input pins. Disabling the Schmitt trigger lowers the power consumption in the I/Os. 424/449 Doc ID 14587 Rev 8...

  • Page 425: Adc Registers

    RM0016 Analog/digital converter (ADC) 24.11 ADC registers 24.11.1 ADC data buffer register x high (ADC_DBxRH) (x=0..7 or 0..9 ) Address offset: 0x00 + 2 * channel number Reset value: 0x00 DBH[7:0] Note: Data buffer registers are not available for ADC2. The data buffer size and base address are device dependent and are specified in the corresponding datasheet.

  • Page 426: Adc Data Buffer Register X Low (Adc_Dbxrl) (X=Or 0

    Analog/digital converter (ADC) RM0016 24.11.2 ADC data buffer register x low (ADC_DBxRL) (x=or 0..7 or 0..9) Address offset: 0x01 + 2 * channel number Reset value: 0x00 DBL[7:0] Note: Data buffer registers are not available for ADC2. The data buffer size and base address are device dependent and are specified in the corresponding datasheet.

  • Page 427: Adc Control/Status Register (Adc_Csr)

    RM0016 Analog/digital converter (ADC) 24.11.3 ADC control/status register (ADC_CSR) Address offset: 0x20 Reset value: 0x00 EOCIE AWDIE CH[3:0] rc_w0 Bit 7 EOC: End of conversion This bit is set by hardware at the end of conversion. It is cleared by software by writing ‘0’.

  • Page 428: Adc Configuration Register 1 (Adc_Cr1)

    Analog/digital converter (ADC) RM0016 24.11.4 ADC configuration register 1 (ADC_CR1) Address offset: 0x21 Reset value: 0x00 SPSEL[2:0] CONT ADON Reserved Reserved Bit 7 Reserved, always read as 0. Bits 6:4 SPSEL[2:0]: Prescaler selection These control bits are written by software to select the prescaler division factor. 000: f MASTER 001: f...

  • Page 429: Adc Configuration Register 2 (Adc_Cr2)

    RM0016 Analog/digital converter (ADC) 24.11.5 ADC configuration register 2 (ADC_CR2) Address offset: 0x22 Reset value: 0x00 EXTTRIG EXTSEL[1:0] ALIGN SCAN Reserved Reserved Reserved Bit 7 Reserved, must be kept cleared. Bit 6 EXTTRIG: External trigger enable This bit is set and cleared by software. It is used to enable an external trigger to trigger a conversion.

  • Page 430: Adc Configuration Register 3 (Adc_Cr3)

    Analog/digital converter (ADC) RM0016 24.11.6 ADC configuration register 3 (ADC_CR3) Address offset: 0x23 Reset value: 0x00 DBUF Reserved rc_w0 Note: This register is not available for ADC2. Bit 7 DBUF: Data buffer enable This bit is set and cleared by software. It is used together with the CONT bit enable buffered continuous mode (DBUF=1, CONT=1).

  • Page 431: Adc Data Register High (Adc_Drh)

    RM0016 Analog/digital converter (ADC) 24.11.7 ADC data register high (ADC_DRH) Address offset: 0x24 Reset value: 0xXX DH[7:0] Bits 7:0 DH[7:0] Data bits high These bits are set/reset by hardware and are read only. When the ADC is in single or non-buffered continuous mode, they contain the high part of the converted data, in right-aligned or left-aligned format depending on the ALIGN bit.

  • Page 432: Adc Schmitt Trigger Disable Register High (Adc_Tdrh)

    Analog/digital converter (ADC) RM0016 24.11.9 ADC Schmitt trigger disable register high (ADC_TDRH) Address offset: 0x26 Reset value: 0x00 TD[15:8] Bits 7:0 TD[15:8] Schmitt trigger disable high These bits are set and cleared by software. When a TDx bit is set, it disables the I/O port input Schmitt trigger of the corresponding ADC input channel x even if this channel is not being converted.

  • Page 433: Adc High Threshold Register High (Adc_Htrh)

    RM0016 Analog/digital converter (ADC) 24.11.11 ADC high threshold register high (ADC_HTRH) Address offset: 0x28 Reset value: 0xFF HT[9:2] Note: This register is not available for ADC2. Bits 7:0 HT[9:2] Analog Watchdog High Voltage threshold MSB These bits are set and cleared by software. They define the MSB of the high threshold (V ) for the Analog Watchdog.

  • Page 434: Adc Low Threshold Register High (Adc_Ltrh)

    Analog/digital converter (ADC) RM0016 24.11.13 ADC low threshold register high (ADC_LTRH) Address offset: 0x2A Reset value: 0x00 LT[9:2] Note: This register is not available for ADC2. Bits 7:0 LT[9:2] Analog watchdog low voltage threshold MSB These bits are set and cleared by software. They define the MSB of the low Threshold (V ) for the Analog Watchdog.

  • Page 435: Adc Watchdog Status Register High (Adc_Awsrh)

    RM0016 Analog/digital converter (ADC) 24.11.15 ADC watchdog status register high (ADC_AWSRH) Address offset: 0x2C Reset value: 0x00 AWS[9:8] Reserved rc_w0 rc_w0 Note: This register is not available for ADC2. Bits 7:2 Reserved, must be kept cleared. Bits 1:0 AWS[9:8] Analog watchdog status flags 9:8 These bits are set by hardware and cleared by software.

  • Page 436: Adc Watchdog Control Register High (Adc_Awcrh)

    Analog/digital converter (ADC) RM0016 24.11.17 ADC watchdog control register high (ADC_AWCRH) Address offset: 0x2E Reset value: 0x00 AWEN[9:8] Reserved Note: This register is not available for ADC2. Bits 7:2 Reserved, must be kept cleared. Bits 1:0 AWEN[9:8] Analog watchdog enable bits 9:8 These bits are set and cleared by software.

  • Page 437: Table 76. Adc1 Register Map And Reset Values

    RM0016 Analog/digital converter (ADC) 24.12 ADC register map and reset values Table 76. ADC1 register map and reset values Address Register name offset ADC1 _DB0RH DATA9 DATA8 0x00 Reset value ADC1_DB0RL DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0x01 Reset value 0x02 to Reserved...

  • Page 438: Table 77. Adc2 Register Map And Reset Values

    Analog/digital converter (ADC) RM0016 Table 76. ADC1 register map and reset values (continued) Address Register name offset ADC1 _LTRH 0x2A Reset value ADC1_LTRL 0x2B Reset value ADC1 _AWSRH AWS9 AWS8 0x2C Reset value ADC1_AWSRL AWS7 AWS6 AWS5 AWS4 AWS3 AWS2 AWS1 AWS0 0x2D...

  • Page 439: Revision History

    RM0016 Revision history Revision history Table 78. Document revision history Date Revision Changes 27-May-2008 Initial release. Updated Section 2: Memory and register map on page introduced high, medium and low density categories; modified end address for option bytes; updated RAM, data EEPROM and Flash program memory densities.

  • Page 440: Table 78. Document Revision History

    Updated Flash program density to 32 - 128 Kbytes for high density STM8S devices in Section 4: Flash program memory and data EEPROM. Updated size of STM8S option byte area in Section 4.4: Memory organization Figure Figure 7, and...
  • Page 441 RM0016 Revision history Table 78. Document revision history (continued) Date Revision Changes Changed note in Section 6.9.2: Software priority register x (ITC_SPRx) on page Updated AWU Section 12.3.2: Time base selection. Removed description of timer input XOR feature (TI1S bit in Section 17 Section Updated trigger selection for and ETR description for TIM5 in...
  • Page 442 Revision history RM0016 Table 78. Document revision history (continued) Date Revision Changes Figure 105: Method 1: transfer sequence diagram for master receiver: Added footnote concerning the next data reception and the EV7event. Bus error (BERR): Updated. Updated Figure 115: TC/TXE behavior when transmitting removed note concerning IDLE preamble.
  • Page 443 Changes Merge with STM8A reference manual (RM0009). Renamed low power modes, Halt, Active-halt, Wait, and Run in the whole document. Added overview of STM8S and STM8A device families on coverpage. Section 2: Boot ROM: added LIN mode configuration. Section 3: Memory and register map: –...

  • Page 444: Figure 101. I 2 C Block Diagram

    Revision history RM0016 Table 78. Document revision history (continued) Date Revision Changes Section 11: General purpose I/O ports (GPIO): – Added note Figure 24: GPIO block diagram. – Removed warning note in Section 11.3: Port configuration and usage. – Updated Table 21: I/O port configuration summary.
  • Page 445 Figure 158: ADC1 block diagram, and note related to AIN12 in Section 24.5.4: Conversion modes. Added value line STM8S devices on page 1 Modified Section 4.4.1: STM8S and STM8A memory organization on page 36 Modified Section 6.6: External interrupts on page 65 Modified TLIS bit description in Section 6.9.4: External interrupt...
  • Page 446 Index RM0016 Index CAN_MIDR4 ......399 CAN_MSR ......386 ADC_AWCRH .
  • Page 447 RM0016 Index IWDG_KR ......124 TIM1_IER ......191 IWDG_PR .
  • Page 448 RM0016 Index UART_GTR ......358 UART_SR ......348 WWDG_CR .
  • Page 449 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.

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