External Clock Register (Clk_Eckr) - ST STM8S Reference Manual

Clock control (CLK)
Bit 0 HSIEN: High speed internal RC oscillator enable
This bit is set and cleared by software. It is set by hardware whenever the HSI oscillator is required,
for example:
–
–
–
It cannot be cleared when HSI is selected as clock master (CLK_CMSR register), as active CCO
source or if the safe oscillator (AUX) is enabled.
0: High-speed internal RC off
1: High-speed internal RC on
9.9.2

External clock register (CLK_ECKR)

Address offset: 0x01
Reset value: 0x00
7 6
Bits 7:2 Reserved, must be kept cleared.
Bit 1 HSERDY: High speed external crystal oscillator ready
This bit is set and cleared by hardware.
0: HSE clock not ready
1: HSE clock ready (HSE clock is stabilized and available)
Bit 0 HSEEN: High speed external crystal oscillator enable
This bit is set and cleared by software. It can be used to switch the external crystal oscillator on or
off. It is set by hardware in the following cases:
–
–
It cannot be cleared when HSE is selected as clock master (indicated in CLK_CMSR register) or as
the active CCO source.
0: HSE clock off
1: HSE clock on
90/449
When activated as safe oscillator by the CSS
When switching to HSI clock (see CLK_SWR register)
When HSI is selected as the active CCO source (see CLK_CCOR register)
5
Reserved
When switching to HSE clock (see CLK_SWR register)
When HSE is selected as the active CCO source (see CLK_CCOR register)
Doc ID 14587 Rev 8
4 3 2 1
HSERDY
r
RM0016
0
HSEEN
rw