External Clock Source Mode 2; Figure 47. External Trigger Input Block Diagram; Figure 48. Control Circuit In External Clock Mode 2 - ST STM8S Reference Manual

16-bit advanced control timer (TIM1)
17.4.4

External clock source mode 2

The counter can count at each rising or falling edge on the ETR. This mode is selected by
writing ECE = 1 in the TIM1_ETR register.
The Figure 47

Figure 47. External trigger input block diagram

ETR pin
Procedure
Use the following procedure to configure the up-counter and, for example, to count once
every two rising edges on the ETR:
1. As no filter is needed in this example, write ETF[3:0] = 0000 in the TIM1_ETR register.
2. Set the prescaler by writing ETPS[1:0] = 01 in the TIM1_ETR register.
3. Select rising edge detection on the ETR pin by writing ETP = 0 in the TIM1_ETR
register.
4. Enable external clock mode 2 by writing ECE = 1 in the TIM1_ETR register.
5. Enable the counter by writing CEN = 1 in the TIM1_CR1 register.
The counter counts once every two ETR rising edges.
The delay between the rising edge on the ETR and the actual reset of the counter is due to
the resynchronization circuit on the external trigger signal (ETRP).

Figure 48. Control circuit in external clock mode 2

COUNTER CLOCK = CK_CNT = CK_PSC
152/449
gives an overview of the external trigger input block.
ETR
0
divider
/1, /2, /4, /8
1
ETP ETPS[1:0]
TIM1_ETR TIM1_ETR
f
MASTER
CNT_EN
ETR
ETRP
ETRF
COUNTER REGISTER
Doc ID 14587 Rev 8
or
ETRP
filter
f
down-counter
MASTER
ETF[3:0]
TIM1_ETR
34
RM0016
TI2F
or
or
TI1F encoder
mode
TRGI external clock
mode 1
ETRF
external clock
mode 2
f
internal clock
MASTER
mode
(internal clock)
ECE SMS[2:0]
TIM1_ETR TIM1_SMCR
35 36
CK_PSC