External Interrupts; Interrupt Instructions; Table 11. Dedicated Interrupt Instruction Set; Figure 16. Nested Interrupt Management - ST STM8S Reference Manual

RM0016

Figure 16. Nested interrupt management

6.6

External interrupts

Five interrupt vectors are dedicated to external Interrupt events:
●
5 lines on Port A: PA[6:2]
●
8 lines on Port B: PB[7:0]
●
8 lines on Port C: PC[7:0]
●
7 lines on Port D: PD[6:0]
●
8 lines on Port E: PE[7:0]
PD7 is the Top Level Interrupt source (TLI), except for 20-pin packages on which the Top
Level Interrupt source (TLI) can be available on the PC3 pin using an alternate function
remapping option bit. Refer to option bytes section in the product datasheet for more details.
To generate an interrupt, the corresponding GPIO port must be configured in input mode
with interrupts enabled. Refer to the register description in the GPIO chapter for details.
The interrupt sensitivity must be configured in the external interrupt control register 1
(EXTI_CR1) and external interrupt control register 2 (EXTI_CR2) (see
Section 6.9.4.).
6.7

Interrupt instructions

Table 11
Table 11. Dedicated interrupt instruction set
Instruction
HALT
IRET
JRM Jump if I1:0=11 (level 3)
IT1
IT2
RIM
IT4
MAIN
11 / 10
shows the interrupt instructions.
New description
Entering Halt mode
Interrupt routine return
Doc ID 14587 Rev 8
TRAP
IT0
IT1
IT3
IT4
Function/example
Pop CCR, A, X, Y, PC
I1:0=11 ?
Interrupt controller (ITC)
SOFTWARE
I1
PRIORITY
LEVEL
3
3
2
1
IT2
3
3
3/0
MAIN
10
Section 6.9.3
I1 H I0 N
1 0
I1 H I0 N
I0
1 1
1 1
0 0
0 1
1 1
1 1
and
Z C
Z C
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