Epson S1R75801F00A Technical Manual page 86

S1R72803F00A
Address Register Name
0x65 IDE_DmaCtl
IDE DMA Control Register
This register makes control when transferring data through the IDE interface.
Bit7..6 Reserved
Bit5 IncFIFOCnt
This bit causes FIFO counter increments to dump the data in the FIFO.
If DMA transfer is aborted, the data remained in the FIFO is discharged to the SRAM.
Operation:
1) Wait if FIFOCnt of the IDE_DmaStat register (0x67) is 3'b010 or higher.
2) When FIFOCnt becomes 3'b001, set IncFIFOCnt to 1 unless TxStreamFull of the BufMonitor register is full.
3) Abort the transfer when FIFOCnt becomes 3'b000.
Bit4 CRC_Clear
Initializes the internal CRC calculation circuit. At start-up of the DMA, even the internal circuits are initialized
. Writing "1" to this bit clears the IDE_CRC0 and IDE_CRC1 Registers.
Bit3 FIFO_Clear
Clears the FIFO for IDE data transfer. Writing "1" to this bit clears the FIFO.
Bit2 IDE_Abort
Use this bit to abort DMA data transfer in execution through the IDE interface. Writing "1" to this bit aborts
the DMA transfer.
Bit1 IDE_Direction
Specifies a data flow direction for DMA data transfer in accordance with the IDE.
IDE_Direction:1 IDE -> SRAM (Buffer)
IDE_Direction:1 IDE <- SRAM (Buffer)
Bit0 DmaStart
Setting this bit to "1" starts DMA transfer between the buffer and the IDE interface.
Address Register Name
0x66 IDE_BusStat
IDE Bus Status Read Register
This register indicates the status of the signal of the IDE interface.
Bit7 DMARQ
Indicates the state of the HDMARQ signal by positive logic.
(The status of the DMARQ_Level bit of the CONFIG0 is reflected.)
Bit6 DMACK
Indicates the state of the XHDMACK signal by positive logic.
Bit5 INTRQ
Indicates the state of the HINTRQ signal by positive logic.
Bit4 IORDY
Indicates the state of the HIORDY signal by positive logic.
Bit3::2 Reserved
Bit1 DIAG
Indicates the state of the XHPDIAG signal by positive logic.
Bit0 DASP
Indicates the state of the XHDASP signal by positive logic.
82
Bit Symbol R/W
7:
6:
5: IncFIFOCnt W
4: CRC_Clear W
3: FIFO_Clear W
2: IDE_Abort W
1: IDE_Direction R/W
0: DmaStart W
Bit Symbol R/W
7: DMARQ
6: DMACK
5: INTRQ
4: IORDY R Indicate IDE I/F Signals State
3:
2:
1: DIAG
0: DASP
Description
0: 1:
0: 1:
0: None 1: Push FIFO Data
0: None 1: CRC Clear
0: None 1: FIFO Clear
0: None 1: IDE Transfer Abort
0: SRAM –> IDE 1: IDE –> SRAM
0: None 1: IDE DMA Start
Description
EPSON
H.Rst S.Rst B.Rst
0x00 0x00 –
H.Rst S.Rst B.Rst
0x00 0x00 –