Epson S1R75801F00A Technical Manual page 51

Address Register Name
0x06 PhyIntStat
PHY Interrupt Status Register
The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become
"1" when the associated bit of the PHYIntEnb Register is "1", this register asserts the interrupt signal to the CPU.
The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read
value again, it clears these bits.
Bit 7 Sub Action Gap Detected
When a Transmit Action Gap is detected in the PHY status of the PHY/LINK interface, this bit becomes "1".
Bit6 Arbitration Reset Gap Detected
When an Arbitration Reset Gap is detected in the PHY status of the PHY/LINK interface, this bit becomes "1".
Bit5 Reserved
Bit4 Reserved
Bit3 Reserved
Bit2 PHY/LINK Interface Interrupt Detected
When a PHY_Interrupt is detected in the PHY status of the PHY/LINK interface, this bit becomes "1".
This status indicates the PHY is put under one of the following.
1) In most instances, a loop is created in the cable topology.
2) Cable power is insufficient.
3) A bias change is detected.
Bit1 PHY Register Write Done
When the write access of the PHY Register is complete, this bit becomes "1".
Bit0 PHY Register Read Done
When read data is stored in the PHYRdStat Register at the time of read access of the PHY Register, this bit
becomes "1".
Address Register Name
0x07 (Reserved)
Bit Symbol R/W
7: SubGap R(W) 0: None
6: ArbGap R(W) 0: None
5:
4:
3:
2: Phy_int R(W) 0: None
1: PhyWrDone R(W) 0: None
0: PhyRdDone R(W) 0: None
Bit Symbol R/W
7:
6:
5:
4:
3:
2:
1:
0:
Description
1: Sub Action Gap Detected
1: ArbtrationResetGapDetected
0: 1:
0: 1:
0: 1:
1: PHY Interrupt Detected
1: PHY Register Write Done
1: PHY Register Read Done
Description
0: 1:
0: 1:
0: 1:
0: 1:
0: 1:
0: 1:
0: 1:
0: 1:
EPSON
S1R72803F00A
H.Rst S.Rst B.Rst
0x00 0x00 –
H.Rst S.Rst B.Rst
0x00 0x00 –
47