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S1R72803F00A
Address
Register Name
0x60
IDE_Config0
0x61
IDE_Config1
0x62
IDE_RegAccCyc 7: Assert Pulse[3]
0x63
IDE_PioDmaCyc 7: Assert Pulse[3]
0x64
IDE_UltraDmaCyc 7:
0x65
IDE_DmaCtl
0x66
IDE_BusStat
0x67
IDE_DmaStat
38
Bit Symbol
R/W
7: UltraDmaMode
0: DMA Mode
6: DmaMode
0: PIO Mode
5: ActPort
0: None
4: IDE_Slave
R/W 0: Master
3: DMARQ_Level
0: Positive Logic
2: Swap
0: Nomal
1:
0:
0:
0:
7: IDE_Reset
R/W 0: None
6:
0:
5:
0:
4:
0:
3:
0:
2: XDIOW_DLYen R/W
0: None
1:
0:
0:
0:
6: Assert Pulse[2] R/W IDE Register Access Strobe Signal Assert Pulse
5: Assert Pulse[1]
Width Minimum Value
4: Assert Pulse[0]
3: Negate Pulse[3]
2: Negate Pulse[2] R/W IDE Register Access Strobe Signal Negate Pulse
1: Negate Pulse[1]
Width Minimum Value
0: Negate Pulse[0]
6: Assert Pulse[2] R/W IDE Transfer Mode Strobe Signal Assert Pulse
5: Assert Pulse[1]
Width Minimum Value
4: Assert Pulse[0]
3: Negate Pulse[3]
2: Negate Pulse[2] R/W IDE Transfer Mode Strobe Signal Negate Pulse
1: Negate Pulse[1]
Width Minimum Value
0: Negate Pulse[0]
0:
6:
0:
5:
0:
4:
0:
3: Cycle Time[3]
2: Cycle Time[2]
R/W IDE Ultra DMA Transfer Mode Strobe Signal
1: Cycle Time[1]
Minimum Cycle Time
0: Cycle Time[0]
7:
0:
6:
0:
5: IncFIFOCnt
W
0: None
4: CRC_Clear
W
0: None
3: FIFO_Clear
W
0: None
2: IDE_Abort
W
0: None
1: IDE_Direction
R/W 0: SRAM –> IDE
0: DmaStart
W
0: None
7: DMARQ
6: DMACK
5: INTRQ
4: IORDY
R
Indicate IDE I/F Signals State
3:
2:
1: DIAG
0: DASP
7: FIFOCnt[2]
R
6: FIFOCnt[1]
R
Indicate word count in FIFO
5: FIFOCnt[0]
R
4:
0:
3:
0:
2:
0:
1: DmaPause
R
0: IDE DMA not Pause 1: IDE DMA Pause
0: DmaRun
W
0: Not DMA
Description
1: Ultra DMA Mode
1: DMA Mode
1: Active
1: Slave
1: Negative Logic
1: Swap IDE Port Hi & Lo
1:
1:
1: IDE Reset
1:
1:
1:
1:
1: Delay XDIOW
1:
1:
1:
1:
1:
1:
1:
1:
1: Push FIFO Data
1: CRC Clear
1: FIFO Clear
1: IDE Transfer Abort
1: IDE –> SRAM
1: IDE DMA Start
1:
1:
1:
1: IDE DMA Running
EPSON
H.Rst S.Rst B.Rst
0x00
0x00
–
0x00
0x00
–
0x00
0x00
–
0x00
0x00
–
0x00
0x00
–
0x00
0x00
–
0x00
0x00
–
0x00
0x00
–
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