Epson S1R75801F00A Technical Manual page 109

9.4.4.2 CPU Write Cycle
P_BCLK
P_A[23:0]
P_CE
X
P_WR _X
X
P_D[15:0]
P_P30
(Wait input)
Symbol
t Address delay time
AD
t P_CEx delay time (1)
CE1
t P_CEx delay time (2)
CE2
t Wait set-up time
WTS
t Wait hold time
WTH
t Write signal delay time (1)
WRD1
t Write data delay time (1)
WDD1
t Write data hold time
WDH
t Write signal delay time (2)
WRD2
t Write signal pulse width
WRW
Regarding the built-in CPU, refer to the S1C33208/204/202 Technical Manual and S1C33 Family ASIC Macro Manual.
In the built-in CPU core, however, a DMA controller or A/D converter are not integrated; this part is different from the
description on the DMA controller and A/D converter given in the Technical Manual and Macro Manual. Both low-
speed oscillation circuit (OSC1) and high-speed oscillation circuit (OSC4) are not available.
C
C
W
1
Next is also wait cycle
t
AD
t
CE1
t
WRD1
t
WDD1
t
t
WTS
WTH
Specification
(Wait cycle) C (Wait cycle)
W
Next is last cycle
t
WRW
t t
t
WTS WTS
WTH
Min.
–
–
–
29
0
–
–
0
–
t (1+WC)–10
CYC
t
* =40ns when bus clock is 25MHz in X2 mode.
CYC
* WC: Wait cycle signal
EPSON
S1R72803F00A
Cn (Last cycle)
t
t
WTH
Max.
8
8
8
–
–
8
10
–
8
–
t
AD
WRD2
t
WDH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
105