Table 50. Rain Max For F Adc = 14 Mhz - STMicroelectronics STM32F038C6 Manual

Electrical characteristics
Symbol
ADC_DR register ready
(2)(4)
W
LATENCY
latency
(2)
t Trigger conversion latency
latr
ADC jitter on trigger
Jitter
ADC
conversion
(2)
Sampling time
t
S
(2)
t Stabilization time
STAB
Total conversion time
(2)
t
CONV
(including sampling time)
1. During conversion of the sampled value (12.5 x ADC clock period), an additional consumption of 100 µA on I
on I should be taken into account.
DD
2. Guaranteed by design, not tested in production.
3. Specified value includes only ADC timing. It does not include the latency of the register access.
4. This parameter specify latency for transfer of the conversion result to the ADC_DR register. EOC flag is set at this time.
Equation 1: R
The formula above
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
T (cycles)
s
1.5
7.5
13.5
70/102
Table 49. ADC characteristics (continued)
Parameter
ADC clock = HSI14
ADC clock = PCLK/2
ADC clock = PCLK/4
f
ADC
f
ADC
f
ADC
max formula
AIN
R
AIN
(Equation 1) is used to determine the maximum external impedance
Table 50. R
DocID026079 Rev 3
Conditions
cycles + 2
f
PCLK
= f /2 = 14 MHz
PCLK
f = f /2
ADC PCLK
= f /4 = 12 MHz
PCLK
f = f /4
ADC PCLK
= f = 14 MHz
HSI14
f = f
ADC HSI14
f = 14 MHz
ADC
-
-
f = 14 MHz,
ADC
12-bit resolution
14 to 252 (t
12-bit resolution
successive approximation)
T
S
<
--------------------------------------------------------------- - R
× × (
f C ln 2
ADC ADC
max for f = 14 MHz
AIN ADC
t (µs)
S
0.11
0.54
0.96
Min Typ
1.5 ADC
1.5 ADC
cycles + 3
-
f
cycles
PCLK
- 4.5
- 8.5
0.196
5.5
0.219
10.5
0.179 -
- 1
0.107 -
1.5 -
14
1 -
for sampling +12.5 for
S
–
ADC
N + 2
)
R max (kΩ)
AIN
0.4
5.9
11.4
STM32F038x6
Max Unit
cycles
f
PCLK
-
cycle
f
PCLK
-
cycle
µs
1/f
PCLK
µs
1/f
PCLK
0.250 µs
- 1/f
HSI14
17.1 µs
239.5 1/f
ADC
1/f
ADC
18 µs
1/f
ADC
and 60 µA
DDA
(1)