Table 59. I 2 S Characteristics; Figure 27. Spi Timing Diagram - Master Mode - STMicroelectronics STM32F038C6 Manual

STM32F038x6
1. Measurement points are done at CMOS levels: 0.3 V
Symbol
f
2
CK
I S clock frequency
1/t
c(CK)
2
t I S clock rise time
r(CK)
2
t I S clock fall time
f(CK)
2
t I S clock high time
w(CKH)
2
t I S clock low time
w(CKL)
t WS valid time
v(WS)
t WS hold time
h(WS)
t WS setup time
su(WS)
t WS hold time
h(WS)
2
I S slave input clock duty
DuCy(SCK)
cycle

Figure 27. SPI timing diagram - master mode

Table 59. I
Parameter
Master mode (data: 16 bits, Audio
frequency = 48 kHz)
Slave mode
Capacitive load C
Master f
frequency = 48 kHz
Master mode
Master mode
Slave mode
Slave mode
Slave mode
DocID026079 Rev 3
and 0.7 V
.
DD DD
2 (1)
S characteristics
Conditions
= 15 pF
L
= 16 MHz, audio
PCLK
Electrical characteristics
Min Max Unit
1.597 1.601
MHz
0 6.5
- 10
- 12
306 -
312 -
2 -
2 -
7 -
0 -
25 75
77/102
ns
%
79