Communication Interfaces; Table 55. Iwdg Min/Max Timeout Period At 40 Khz (Lsi); Table 56. Wwdg Min/Max Timeout Value At 48 Mhz (Pclk) - STMicroelectronics STM32F038C6 Manual

Electrical characteristics
Prescaler divider
/16
/32
/64
/128
/256
1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Prescaler
1
2
4
8
6.3.19

Communication interfaces

2
I C interface characteristics
2
The I C interface meets the timings requirements of the I
manual rev. 03 for:
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
•
Fast-mode (Fm): with a bit rate up to 400 kbit/s
•
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
2
The I C timings requirements are guaranteed by design when the I2Cx peripheral is
properly configured (refer to Reference manual).
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not "true" open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and V
support Fm+ low level output current maximum requirement. Refer to
port characteristics
2
All I C SDA and SCL I/Os embed an analog filter. Refer to the table below for the analog
filter characteristics:
74/102

Table 55. IWDG min/max timeout period at 40 kHz (LSI)

PR[2:0] bits
/4 0
/8 1
2
3
4
5
6 or 7

Table 56. WWDG min/max timeout value at 48 MHz (PCLK)

WDGTB
0
1
2
3
2
for the I C I/Os characteristics.
Min timeout RL[11:0]=
0x000
0.1
0.2
0.4
0.8
1.6
3.2
6.4
Min timeout value
0.0853
0.1706
0.3413
0.6826
is disabled, but is still present. Only FTf I/O pins
DDIOx
DocID026079 Rev 3
STM32F038x6
(1)
Max timeout RL[11:0]=
0xFFF
409.6
819.2
1638.4
3276.8
6553.6
13107.2
26214.4
Max timeout value
5.4613
10.9226
21.8453
43.6906
2
C-bus specification and user
Section 6.3.13: I/O
Unit
ms
Unit
ms