Cisco ONS 15454 Reference Manual page 270

5.11 5.11 CE-100T-8 Card
The CE-100T8 card also supports the link capacity adjustment scheme (LCAS), which allows hitless
dynamic adjustment of SONET link bandwidth. The CE-100T-8 card's LCAS is hardware-based, but the
CE-100T-8 also supports SW-LCAS. This makes it compatible with the ONS 15454 SDH ML-Series
card, which supports only SW-LCAS and does not support the standard hardware-based LCAS.
SW-LCAS is supported when a circuit from the CE-100T-8 terminates on the ONS 15454 SDH
ML-Series card.
The circuit types supported are:
HO-CCAT
•
LO-VCAT with no HW-LCAS
•
LO-VCAT with HW-LCAS
•
STS-1-2v SW-LCAS with ML only.
•
Each 10/100 Ethernet port can be mapped to a SONET channel in increments of VT1.5 or STS-1
granularity, allowing efficient transport of Ethernet and IP over the SONET infrastructure.
Figure 5-10
Figure 5-10
CE100T
8
FAIL
ACT
1
2
3
4
5
6
7
8
CONSOLE
The following paragraphs describe the general functions of the CE-100T-8 card and relate to the block
diagram.
In the ingress direction, (Ethernet-to-SONET), the PHY, which performs all of the physical layer
interface functions for 10/100 Mbps Ethernet, sends the frame to the network processor for queuing in
the respective packet buffer memory. The network processor performs packet processing, packet
Cisco ONS 15454 Reference Manual, R7.0.1
5-26
shows the CE-100T-8 card faceplate and block diagram.
CE-100T-8 Faceplate and Block Diagram
Packet Buffer
3x0.5MB
8x
Packet
10/100BaseT Octal
SMII
Processor/
RJ45 PHY 8
Switch
Fabric
Control Mem
1x2MB
Part of qMDM FPGA
4 SMII ETS
#1
STS3
ETS
4 SMII
#2
STS3
STS3
4 SMII
ETS
#3
1
STS3
3 SMII
ETS
#4
SMII
Option
qMDM
FPGA
MII
FCC3
Chapter 5 Ethernet Cards
SDRAM
SDRAM
Add_Bus
qMDM
STS12 BTC
Drop_Bus
FPGA
SDRAM
SDRAM
SCC1
60x
CPU
SDRAM
Flash
128MB
8MB
nVRAM
B
a
c
k
p
l
a
n
e
CPLD
OL-9217-01