Intel i86W Manual page 123

FLOATING-POINT INSTRUCTIONS
Figure 6-8 illustrates
faddp
when PS is set for 32-bit pixels. Since
faddp
adds 32-bit
values in this case, each value can be treated as a fixed-point real number with an 8-bit
integer portion and an 24-bit fractional portion. The real numbers are rounded to 8 bits
by truncation when they are loaded into the MERGE register. With each
faddp,
the '
MERGE register is shifted right by 8 bits. Normally, three
faddp
instructions are exe-
cuted consecutively, one for each color represented in a pixel. The shifting of MERGE
causes the results of consecutive
faddp
instructions to be accumulated in the MERGE
register.
63
47
31
15
0
INT FRACTION
INT
FRACTION I
brc1
++++++ ++++++ ++++++
++++++
63
47 31 15 0
INT FRACTION INT
FRACTION
fsrc2
o
INT
FRACTION
INT
FRACTION
fdest
o
MERGE
240329i
Figure 6-8. FADDP with 32-Bit Pixels
6-35