Intel i86W Manual page 92

FLOATING·POINT INSTRUCTIONS
Changing the FZ (flush zero), RM (rounding mode), or RR (result register) bits of
fsr
while there are results in either the multiplier or adder pipeline produces effects that are
not defined.
6.2.1 Scalar Mode
In addition to the pipelined execution mode described above, the i860 microprocessor
also can execute floating-point instructions in "scalar" mode. Most floating-point
instructions have both pipe lined and scalar variants, distinguished by a bit in the instruc-
tion encoding. In scalar mode, the floating-point unit does not start a new operation
until the previous floating-point operation is completed. The scalar operation passes
through all stages of its pipeline before a new operation is introduced, and the result is
stored automatically. Scalar mode is used when the next operation depends on results
from the previous few floating-point operations (or when the compiler or programmer
does not want to deal with pipelining).
6.2.2 Pipelining Status Information
Result status information in the
fsr
consists of the AA, AI, AO, AU, and AE bits, in the
case of the adder, and the MA, MI, MO, and MU bits, in the case of the mUltiplier. This
information arrives at the fsr via the pipeline in one of two ways:
1. It is calculated by the last stage of the pipeline. This is the normal case.
2. It is propagated from the first stage of the pipeline. This method is used when
restoring the state of the pipeline after a preemption. When a store instruction
updates the
fsr
and the the U bit being written into the
fsr
is set, the store updates
result status bits in the first stage of both the adder and multiplier pipelines. When
software changes the result-status bits of the first stage of a particular unit (multi-
plier or adder), the updated result-status bits are propagated one stage for each
pipelined floating-point operation for that unit. In this case, each stage of the adder
and muitipiier pipeiines hoids its own copy of tht! rdevant bits of the
fsf.
'vVheil they
reach the last stage, they override the normal result-status bits computed from the
last-stage result.
At the next floating-point instruction (or at certain core instructions), after the result
reaches the last stage, the i860 microprocessor traps if any of the status bits of the fsr
indicate exceptions. Note that the instruction that creates the exceptional condition is
not the instruction at which the trap occurs.
6.2.3 Precision in the Pipelines
In pipelined mode, when a floating-point operation is initiated, the result of an earlier
pipelined floating-point operation is returned. The result precision of the current in-
struction applies to the operation being initiated. The precision of the value stored in
fdest is that which was specified by the instruction that initiated that operation.
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