Intel i86W Manual page 82

CORE INSTRUCTIONS
5.12 CONTROL REGISTER ACCESS
Id.c csrc2, idest
idest ~ csrc2
st.c isrc1 ni, csrc2
csrc2
~
isrc1ni
(Load from control register)
(Store to control register)
Csrc2 specifies a control register that is transferred to or from a general-purpose regis-
ter. The function of each control register is defined in Chapter 3. As shown below, some
registers or parts of registers are write-protected when the U-bit in the
psr
is set. A store
to those registers or bits is ignored when the i860 microprocessor is in user mode. The
encoding of csrc2 is defined by Table 5-1.
Programming Notes
Saving
fir
(the fault instruction register) anytime except the first time after a trap occurs
saves the address of the
Id.c
instruction.
After a scalar floating-point operation, a
st.c
to
fsr
should not change the value of RR,
RM, or FZ until the point at which result exceptions are reported. (Refer to Chapter 7
for more details.)
Only a trap handler should use the intruction
st.c
to set the trap bits (IT, IN, IAT, DAT,
FT) of the
psr.
Table 5-1. Control Register Encoding for Assemblers
Register
Src2Code
User-Mode
Write-Protected?
fir (Fault Instruction)
0 N/A***
psr (Processor Status)
1
Yes*
dirbase
(Directory Base)
2
Yes
db (Data Breakpoint)
3
,,--
It:::~
fsr (Floating-Point Status)
4
No
epsr
(Extended Process Status) 5 Yes**
* Only the psr bits BR,BW, PIM, 1M, PU, U, IT, IN, IAT, DATA, FT, OS, DIM, and KNF are write-protected.
** The processor type, stepping number, and cache size cannot be changed from either user or
supervisor level.
*** The fir register cannot be written by the st.c instruction.
5-20