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TRAPS AND INTERRUPTS
4. The
fsr.
5. The
dirbase
register.
6. The MERGE register.
7. The KR, Kl, and T registers.
8. Any of the four pipeJines (refer to Section 7.9).
9. The floating-point and integer register files.
7.2.2 Inside the Trap Handler
While most activities of trap handlers are application dependent (and, therefore, are
beyond the scope of this manual), programmers should be aware of the following
requirements that are imposed by the i860 microprocessor architecture:
1. For all types of traps, the trap handler must check the IL bit of
epsr
to determine if
a locked sequence is being interrupted.
2. The trap handler must execute
Id.e fir,
isrcl
once for each trap. Failure to do so
prevents
fir
from receiving the address of the next trap.
7.2.3 Returning from the Trap Handler
Returning from a trap handler involves the following steps:
1. Restoring the pipeline states, including the
fsr,
KR, Kl, T, and MERGE registers,
where necessary.
2. Subtracting srcl from src2, when a data-access fault occurred on an auto increment-
ing load/store instruction and a floating-point trap did not also occur.
3. Determining where to resume execution by inspecting the instruction at
fir -
4. The
details for this determination are given in Section 7.2.3.1.
4. Restoring the integer and floating-point register 'files (except for the register that
holds the resumption address).
5. Updating
psr
with the value to be used after return.
It
may be necessary to set the
KNF bit in
psr.
The requirements for KNF are given in Section 7.2.3.2. The trap
handler must ensure that no trap occurs between the
st.e
to the
psr
and the indirect
branch that exits the trap handler.
7-3
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