Intel i86W Manual page 140

TRAPS AND INTERRUPTS
2. Result exceptions. This class includes the overflow, underflow, and inexact excep-
tions defined by the IEEE standard.
Software available from Intel provides the IEEE standard default handling for all these
exceptions.
The floating-point fault occurs only on floating-point instructions, and on
pst, fst, fld,
pfld,
and
ixfr.
No floating-point fault occurs when
pst, fst, fld, pfld,
or
ixfr
transfers an
operand that is not a valid floating-point value.
7.4.1 Source Exception Faults
When used as inputs to the floating-point adder or multiplier, all exceptional operands
(including infinities, denormalized numbers and NaNs) cause a floating-point fault and
set SE in the
fsr.
Source exceptions are reported on the instruction that initiates the
operation. For pipelined operations, the pipeline is not advanced. The trap handler can
reference both source operands and the operation by decoding the instruction specified
by
fir.
In the case of dual operations, the trap handler has to determine which special registers
the source operands are stored in and inspect all four source operands to see if one or
both operations need to be fixed up. It can then compute the appropriate result and
store the result in [des!, in the case of a scalar operation, or replace the appropriate
first-stage result, in the case of a pipe lined operation.
Note that, in the following sequence, inappropriate use of the FTE bit of the
fsr
can
produce an invalid operand that does not cause a source exception:
1. Floating-point traps are masked by clearing the FTE bit.
2.
An dual-operation instruction causes underflow or overflow leaving an invalid result
in the T register.
3. Floating-point traps are enabled by setting the FTE bit.
4. The invalid result in the T register is used as an operand of a subsequent instruction.
Even though the result of an operation would normally cause a source exception, it can
be inserted into the pipeline as follows:
1. Disable traps by clearing FTE.
2. Perform a pipelined add of the value with zero or a multiply by one.
3. Set the result-status bits of
fsr
to "normal" by loading
fsr
with the U-bit set and
zeros in the appropriate unit's result-status bits. The other unit's status must be set
to the saved status for the first pipeline stage.
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