Intel i86W Manual page 145

TRAPS AND INTERRUPTS
7.9.3 Graphics Pipeline
The graphics pipeline has only one stage. To flush the pipeline, execute a
pfiadd fO, fO,
Idest. The only other state information for the graphics unit resides in the PM bits of
psr,
the IRP bit of the
fsr,
and in the MERGE register. Store the MERGE register with a
form
instruction. Restore the MERGE register by using
faddz
instructions (see
Example 7-2).
7.9.4 Examples of Pipeline Preemption
Example 7-1 shows how to save the pipeline state.
Example 7-2 shows how to restore the pipeline state. Trap handlers manipulate the
result-status bits in the floating-point pipelines while preparing for pipeline resumption.
When storing to
fsr
with the U-bit set, the result-status bits are loadeq into the first stage
of the pipelines of the floating-point adder and multiplier. The updated result-status bits
of a particular unit (multiplier or adder) are propagated one stage for each pipelined
floating-point operation for that unit. When they reach the last stage, they override the
normal result-status bits computed from the last-stage result. The result-status bits in the
fsr
always reflect the last-stage result status and cannot be directly set by software.
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