Intel i86W Manual page 24

ARCHITECTURAL OVERVIEW
1.6 CACHES
In addition to the page translation cache mentioned previously, the i860 microprocessor
contains separate on-chip caches for data and instructions. Caching is transparent, ex-
cept to systems programmers who must ensure that the data cache is flushed when
switching tasks or changing system memory parameters. The on-chip cache controller
also provides the interface to the external bus with a pipelined structure that allows up
to three outstanding bus cycles.
The instruction cache is a two-way, set-associative memory of four Kbytes, with 32-byte
blocks. The data cache is a write-back cache, composed of a two-way, set-associative
memory of eight Kbytes, with 32-byte blocks.
1.7 PARALLEL ARCHITECTURE
The i860 microprocessor offers a high level of parallelism in a form that is flexible
enough to be applied to a wide variety of processing styles:
• Conventional programs and conventional compilers can use the i860 microprocessor
as a scalar machine and still benefit from its high-performance. Even when used as a
scalar machine, the i860 microprocessor implements concurrency between integer and
floating-point operations, as long as there are no conflicts for internal resources. An
integer instruction that follows a floating-point instruction begins immediately, over-
lapping the floating-point instruction. A floating-point instruction that follows an in-
teger instruction also begins immediately.
• Compilers designed for the vector model can treat the i860 microprocessor as a vector
machine.
• New instruction-scheduling technology for compilers can compare the processing re-
quirements and data dependencies of programs with the available resources of the
i860 microprocessor, and can take maximum advantage of its dual-instruction mode,
pipelining, and caching.
An established compiler technology for the vector model of computation already exists.
This technology can be applied directly to the i860 microprocessor. The key to treating
the i860 microprocessor as a vector machine is choosing the appropriate vector primi-
tives that the compiler assumes are available on the target machine. (Intel has defined a
standard set of vector primitives.) The vector primitives are implemented as hand-coded
subroutines; the compiler generates calls to these subroutines. If a compiler depends on
the traditional concept of vector registers, it can implement them by mapping these
registers to specific memory addresses. By virtue of frequent access to these addresses,
the simulated registers will reside permanently in the data cache.
Existing programs can be upgraded to take better advantage of the parallel architecture
of the i860 microprocessor using vector-oriented technology. Flow analysis or "vectoriz-
ing" tools can identify parallelism that is implicit in existing programs. When modified
(either manually or automatically) and compiled by an appropriate compiler for the i860
microprocessor, these programs can achieve an even greater performance gain from the
i860 microprocessor.
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