Intel i86W Manual page 59

ADDRESSING
1. Read the PTE (page table entry) at the physical address formed by DTB:DIR:OO.
Note that the data cache is not accessed during PTE fetches; therefore, the operat-
ing system must ensure that the page table is not in the cache.
2. If P in the PTE is zero, generate a data- or instruction-access fault.
3. If W in the PTE is zero, the operation is a write, and either the U bit of the PSR is
set or WP = 1, generate a data-access fault.
4. If the U bit in the PTE is zero and the U bit in the psr is set, generate a data- or
instruction-access fault.
5. If A in the PTE is zero and if the TLB miss occurred while the bus was locked,
generate a data- or instruction-access fault. (The trap allows software to set A to
one and restart the sequence. This avoids ambiguity in determining what address
corresponds to a locked semaphore for external bus hardware use.)
6. If A in the PTE is zero and if the TLB miss occurred while the bus was not locked,
assert LOCK#, refetch the PTE, set A, and store the PTE, deasserting LOCK#
during the store.
7. Locate the PTE at the physical address formed by PFA1:PAGE:00.
8. Perform the P, A, W, and U checks as in steps 3 through 6 with the second-level
PTE.
9. If D in the PTE is clear and the operation is a write, generate a data-access fault.
10. Form the physical address as PFA2:0FFSET.
4.2.6 Address Translation Faults
An address translation fault can be signalled as either an instruction-access fault or a
data-access fault. (Refer to Chapter 7 for more information on this and other faults.)
The instruction causing the fault can be reexecuted by the return-from-trap sequence
defined in Chapter 7.
4.2.7 Page Translation Cache
For greatest efficiency in address translation, the i860 microprocessor stores the most
recently used page-table data in an on-chip cache called the TLB (translation lookaside
buffer). Only if the necessary paging information is not in the cache must both levels of
page tables be referenced.
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