Intel Arria 10 series Manuals

Manuals and User Guides for Intel Arria 10 series. We have 3 Intel Arria 10 series manuals available for free PDF download: User Manual

Intel Arria 10 series User Manual (607 pages)

Transceiver PHY

Brand: Intel | Category: Transceiver | Size: 4.99 MB

User Guide
1
Table of Contents
2
1 Arria ® 10 Transceiver PHY Overview

8
2 Implementing Protocols in Arria 10 Transceivers

32
3 Plls and Clock Networks

347
- Plls
  349
  - Transmit Plls Spacing Guideline When Using ATX Plls and Fplls
    349
  - Atx Pll
    350
  - Fpll
    359
  - Cmu Pll
    368
- Input Reference Clock Sources
  372
- Transmitter Clock Network
  375
  - X1 Clock Lines
    376
  - X6 Clock Lines
    377
  - Xn Clock Lines
    379
  - GT Clock Lines
    381
- Clock Generation Block
  383
- FPGA Fabric-Transceiver Interface Clocking
  384
- Transmitter Data Path Interface Clocking
  386
- Receiver Data Path Interface Clocking
  387
- Unused/Idle Clock Line Requirements
  389
- Channel Bonding
  389
  - PMA Bonding
    389
  - PMA and PCS Bonding
    391
  - Selecting Channel Bonding Schemes
    392
  - Skew Calculations
    393
- PLL Feedback and Cascading Clock Network
  393
- Using Plls and Clock Networks
  398
  - Non-Bonded Configurations
    398
  - Bonded Configurations
    403
  - Implementing PLL Cascading
    408
  - MIX and Match Example
    409
  - Timing Closure Recommendations
    413
- Plls and Clock Networks Revision History
  414
4 Resetting Transceiver Channels

416
5 Arria 10 Transceiver PHY Architecture

447
- Arria 10 PMA Architecture
  447
  - Transmitter
    447
  - Transmitter Buffer
    448
  - Receiver
    450
  - Receiver Buffer
    451
  - Loopback
    460
- Arria 10 Enhanced PCS Architecture
  461
  - Transmitter Datapath
    462
  - Receiver Datapath
    471
- Arria 10 Standard PCS Architecture
  479
  - Transmitter Datapath
    480
  - Byte Serializer
    481
  - Receiver Datapath
    485
  - Byte Deserializer
    493
- Arria 10 PCI Express Gen3 PCS Architecture
  495
  - Transmitter Datapath
    496
  - Receiver Datapath
    497
  - PIPE Interface
    498
- Intel Arria 10 Transceiver PHY Architecture Revision History
  499
6 Reconfiguration Interface and Dynamic Reconfiguration

502
7 Calibration

567
- Reconfiguration Interface and Arbitration with Presice Calibration Engine
  567
- Calibration Registers
  569
  - Avalon-MM Interface Arbitration Registers
    569
  - Transceiver Channel Calibration Registers
    570
  - Fractional PLL Calibration Registers
    570
  - ATX PLL Calibration Registers
    571
  - Capability Registers
    571
  - Rate Switch Flag Register
    573
- Power-Up Calibration
  574
- User Recalibration
  576
  - Recalibration after Transceiver Reference Clock Frequency or Data Rate Change
    579
- Calibration Example
  581
  - ATX PLL Recalibration
    581
  - Fractional PLL Recalibration
    581
  - CDR/CMU PLL Recalibration
    582
  - PMA Recalibration
    582
- Calibration Revision History
  583
8 Analog Parameter Settings

585
- Making Analog Parameter Settings Using the Assignment Editor
  585
- Updating Quartus Settings File with the Known Assignment
  585
- Analog Parameter Settings List
  586
- Receiver General Analog Settings
  588
  - Xcvr_A10_Rx_Link
    588
  - Xcvr_A10_Rx_Term_Sel
    589
  - Xcvr_Vccr_Vcct_Voltage - Rx
    589
- Receiver Analog Equalization Settings
  590
  - CTLE Settings
    590
  - VGA Settings
    593
  - Decision Feedback Equalizer (DFE) Settings
    594
- Transmitter General Analog Settings
  596
  - Xcvr_A10_Tx_Link
    596
  - Xcvr_A10_Tx_Term_Sel
    597
  - Xcvr_A10_Tx_Compensation_En
    597
  - Xcvr_Vccr_Vcct_Voltage - Tx
    598
  - Xcvr_A10_Tx_Slew_Rate_Ctrl
    599
- Transmitter Pre-Emphasis Analog Settings
  600
- Transmitter VOD Settings
  604
  - Xcvr_A10_Tx_Vod_Output_Swing_Ctrl
    604
- Dedicated Reference Clock Settings
  605
  - Xcvr_A10_Refclk_Term_Tristate
    605
  - Xcvr_A10_Tx_Xtx_Path_Analog_Mode
    606

Intel Arria 10 series User Manual (121 pages)

SoC Development Kit

Brand: Intel | Category: Microcontrollers | Size: 7.99 MB

Table of Contents
2
1 Intel ® Arria ® 10 Soc Development Kit Overview

4
2 Getting Started

10
3 Development Board Setup

15
- Applying Power to the Board
  15
- Default Switch and Jumper Settings
  16
4 Board Test System

20
- Preparing the Board
  21
- Running the Board Test System
  22
- Version Selector
  22
- Using the Board Test System
  24
  - Using the Configure Menu
    24
  - The System Info Tab
    26
  - The GPIO Tab
    27
  - The XCVR Tab
    28
  - The Pcie Tab
    30
  - The FMCA Tab
    33
  - The FMCB Tab
    36
  - The DDR3 Tab
    40
  - The DDR4 Tab
    42
  - The EEPROM Tab
    43
  - The Power Monitor
    44
  - The Clock Control
    46
5 Board Components

48
- Board Overview
  48
- Featured Device: Arria 10 Soc
  51
- MAX V CPLD 5M2210 System Controller
  52
- Configuration
  60
- Status Elements
  64
- Setup Elements
  64
  - Board Settings DIP Switch
    64
  - JTAG Chain Control DIP Switch
    65
  - Reference Clock Source Selection
    67
  - CPU Reset Push Button
    67
  - Logic Reset Push Button
    67
- General User Input/Output
  67
  - Character LCD
    68
- Clock Circuitry
  69
  - On-Board Oscillators
    69
- Components and Interfaces
  70
  - PCI Express
    70
  - 10/100/1000 Ethernet (HPS)
    72
  - 10/100/1000 Ethernet (FPGA)
    74
  - Fmc
    75
  - HPS Shared I/O
    88
  - USB 2.0 Port (HPS)
    90
  - Uart (Hps)
    90
  - Real-Time Clock (HPS)
    91
  - Sfp
    91
  - I C Interface
    92
  - FPGA General I/O Configuration
    93
  - HPS SPIO Interface
    100
- Memory
  105
  - FPGA External Memory
    106
  - HPS External Memory
    112
  - HPS Boot Flash Interface
    115
  - C Eeprom
    115
  - Daughtercards
    116
- Board Power Supply
  117
  - Power Distribution System
    118
  - Power Measurement
    118
Additional Information

119
- Document Revision History for the Intel Arria 10 Soc Development Kit User Guide
  119
- Compliance and Conformity Statements
  121
  - CE EMI Conformity Caution
    121

Intel Arria 10 series User Manual (43 pages)

FPGA HDMI Design Example

Brand: Intel | Category: Motherboard | Size: 0.38 MB

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Intel Arria 10 series User Manual (607 pages)

Table of Contents

1 Arria ® 10 Transceiver PHY Overview

2 Implementing Protocols in Arria 10 Transceivers

3 Plls and Clock Networks

4 Resetting Transceiver Channels

5 Arria 10 Transceiver PHY Architecture

6 Reconfiguration Interface and Dynamic Reconfiguration

7 Calibration

8 Analog Parameter Settings

Intel Arria 10 series User Manual (121 pages)

Table of Contents

1 Intel ® Arria ® 10 Soc Development Kit Overview

2 Getting Started

3 Development Board Setup

4 Board Test System

5 Board Components

Additional Information

Intel Arria 10 series User Manual (43 pages)

Table of Contents

Arria ® 10 Devices

1 Intel ® FPGA HDMI Design Example Quick Start Guide for Intel

2 Intel FPGA HDMI Design Example Detailed Description

A Intel FPGA HDMI Design Example User Guide for Intel Arria 10 Devices Archives

B Revision History for Intel FPGA HDMI Design Example User Guide for Intel Arria 10 Devices

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