Arria 10 Transceiver Register Map; Reconfiguration Interface And Dynamic Revision History - Intel Arria 10 User Manual

6.19. Arria 10 Transceiver Register Map

The transceiver register map provides a list of available PCS, PMA, and PLL addresses
that are used in the reconfiguration process.
Use the register map in conjunction with a transceiver configuration file generated by
the Arria 10 Native PHY IP core. This configuration file includes details about the
registers that are set for a specific transceiver configuration. Do not use the register
map to locate and modify specific registers in the transceiver. Doing so may result in
an illegal configuration. Refer to a valid transceiver configuration file for legal register
values and combinations.
The register map is provided as an Excel spreadsheet for easy search and filtering.
Related Information
Arria 10 Transceiver Register Map

6.20. Reconfiguration Interface and Dynamic Revision History

Document
Version
2018.06.15 Made the following change:
• Added instructions on how to enable the Transceiver Toolkit capability in the Native PHY IP to
Dynamic Reconfiguration Parameters.
2017.11.06 Made the following changes:
• Updated the note in "Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow" topic to "The
PMA analog settings are governed by a set of rules. Not all combinations of V
are valid. Please refer to Arria 10 Pre-Emphasis and Output Swing Settings for current valid
settings. Also, refer to "Analog Parameter Settings" and setup guidelines on post_tap polarity
settings."
• Updated the description of bit [25:16] in table "Mapping of SystemVerilog Configuration File Line" to
"DPRIO address. Refer to Intel Arria 10 Transceiver Register Map for details of the address."
•
Changes the configurations file path to "
type>_a10_<quartus version>\synth\reconfig
• Added Examples 1 and 2 in "fPLL Reference Clock Switching" topic.
2016.10.31 Made the following changes:
• "VGA" PMA Analog Feature added in "PMA Analog Settings that are Channel or System Dependent"
table.
• Updated the value of AC Gain Control of High Gain Mode CTLE parameter to
radp_ctle_acgain_4s_0 to radp_ctle_acgain_4s_28 in the "Analog PMA Settings (Optional) for
Dynamic Reconfiguration" table.
• Updated the value of Slew Rate Control parameter to slew_r0 to slew_r5 in the "Analog PMA
Settings (Optional) for Dynamic Reconfiguration" table.
2016.05.02 Made the following changes
• Removed the topic "On-Die Instrumentation" and related information from the user guide.
• Edited "Native PHY IP" with "Native PHY IP and ATX PLL IP" wherever necessary.
• Edited "Embedded Reconfiguration Steamer" topic.
• Edited the "Arbitration" topic.
• Edited the "Using PRBS and Square Wave Data Pattern Generator and Checker" for bonded as well
as non bonded designs. Also added all the examples for each case.
• Updated "Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow" topic.
2015.12.18 Made the following changes:
® ®
Intel Arria 10 Transceiver PHY User Guide
564
6. Reconfiguration Interface and Dynamic Reconfiguration
Changes
<IP instance name>\altera_xcvr_<IP
".
UG-01143 | 2018.06.15
and pre-emphasis
OD
continued...