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UG-20077 | 2017.11.06
2 Intel FPGA HDMI Design Example Detailed Description
The Intel FPGA HDMI IP core design example demonstrates one HDMI instance parallel
loopback consisting three RX channels and four TX channels.
Table 6.
Intel FPGA HDMI Design Example for Intel Arria 10 Devices
Design Example
Arria 10 HDMI RX-TX Retransmit
Features
•
The design instantiates FIFO buffers to perform a direct HDMI video stream
passthrough between the HDMI sink and source.
•
The design uses LED status for early debugging stage.
•
The design comes with RX and TX only options.
•
The design demonstrates the insertion and filtering of Dynamic Range and
Mastering (HDR) InfoFrame in RX-TX link module.
•
The design demonstrates the management of EDID passthrough from an external
HDMI sink to an external HDMI source when triggered by a TX hot-plug event.
•
The design uses push-button controlled HDMI TX core signals:
—
mode
—
info_avi[47]
auxiliary packet transmission through sidebands or auxiliary data ports
The RX instance receives a video source from the external video generator, and the
data then goes through a loopback FIFO before it is transmitted to the TX instance.
You need to connect an external video analyzer, monitor, or a television with HDMI
connection to the TX core to verify the functionality.
2.1 HDMI RX-TX Retransmit Design Example
The HDMI RX-TX retransmit design example demonstrates parallel loopback on
simplex channel mode for Intel FPGA HDMI IP core.
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Data Rate
< 6,000 Mbps
signal to select DVI or HDMI encoded video frame
,
info_vsi[61]
Channel Mode
Simplex
, and
audio_info_ai[48]
Loopback Type
Parallel with FIFO buffer
signals to select
ISO
9001:2008
Registered
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