Compile The Design; Verify Design Functionality; Arria 10 Transceiver Protocols And Phy Ip Support - Intel Arria 10 User Manual

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Related Information
• Analog Parameter Settings
• Arria 10 Pin Connection Guidelines

2.2.12. Compile the Design

To compile the transceiver design, add the <phy_instancename>.qip files for all the IP
blocks generated using the IP Catalog to the Quartus Prime project library. You can
alternatively add the .qsys and .qip variants of the IP cores.
Note: If you add both the .qsys and the .qip file into the Quartus Prime project, the
software generates an error.
Related Information
Intel Quartus Prime Incremental Compilation for Hierarchical and Team-Based Design
For more information about compilation details.

2.2.13. Verify Design Functionality

Simulate your design to verify the functionality of your design. For more details, refer
to Simulating the Native Transceiver PHY IP Core section.
Related Information
• Simulating the Transceiver Native PHY IP Core
• Quartus Prime Handbook - Volume 3: Verification
Information about design simulation and verification.

2.3. Arria 10 Transceiver Protocols and PHY IP Support

Table 8. Arria 10 Transceiver Protocols and PHY IP Support
Protocol
PCIe Gen3 x1, x2, x4,
x8
PCIe Gen2 x1, x2, x4,
x8
PCIe Gen1 x1, x2, x4,
x8
(9)
For more information about Transceiver Configuration Rules, refer to Using the Intel Arria
10Transceiver Native PHY IP Core section.
(10)
For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver
Native PHY IP Core section.
(11)
Hard IP for PCI Express is also available as a separate IP core.
on page 585
Transceiver PHY IP PCS Support
Core
Native PHY IP core Standard and Gen3
(PIPE)/Hard IP for PCI
(11)
Express
Native PHY IP (PIPE)
core/Hard IP for PCI
(11)
Express
Native PHY IP (PIPE)
core/Hard IP for PCI
(11)
Express
on page 325
Transceiver
Configuration Rule
Gen3 PIPE
Standard Gen2 PIPE
Standard Gen1 PIPE
®
Intel
Protocol Preset
(9)
PCIe PIPE Gen3 x1
PCIe PIPE Gen3 x8
PCIe PIPE Gen2 x1
PCIe PIPE Gen2 x8
User created
continued...
®
Arria 10 Transceiver PHY User Guide
(10)
41