Intel ® Fpga Hdmi Design Example Quick Start Guide For Intel - Intel Arria 10 series User Manual

Figure 2. Directory Structure for the Design Example
quartus
db (Standard)/qdb (Pro)
incremental_db (Standard)
output_files
tmp-clearbox (Pro)
a10_hdmi_demo.qpf
a10_hdmi_demo.qsf
Table 1. Generated RTL Files
Folders
gxb
hdmi_rx
hdmi_tx
®
Intel FPGA HDMI Design Example User Guide for Intel
4
®
1 Intel FPGA HDMI Design Example Quick Start Guide for Intel
<Design Example>
rtl
a10_hdmi2_demo.v
a10_reconfig_arbiter.sv
clock_control.qsys/clock_control.ip
clock_crosser.v
nios.qsys
rxtx_link.v
gxb
hdmi_rx
hdmi_tx
i2c_master
i2c_slave
pll
reconfig_mgmt
sdc
hdr
common (Pro)
•
/gxb_rx.qsys
•
(Intel Quartus Prime Pro Edition)
/gxb_rx.ip
•
/gxb_rx_reset.qsys
•
/gxb_rx_reset.ip
•
/gxb_tx.qsys
•
(Intel Quartus Prime Pro Edition)
/gxb_tx.ip
•
/gxb_tx_fpll.qsys
•
/gxb_tx_fpll.ip
•
/gxb_tx_reset.qsys
•
/gxb_tx_reset.ip
•
/hdmi_rx.qsys
•
(Intel Quartus Prime Pro Edition)
/hdmi_rx.ip
/hdmi_rx_top.v
/mr_clock_sync.v
/mr_hdmi_rx_core_top.v
/mr_rx_oversample.v
/symbol_aligner.v
•
/hdmi_tx.qsys
•
(Intel Quartus Prime Pro Edition)
/hdmi_tx.ip
/hdmi_tx_top.v
®
Arria 10 Devices
simulation script
build_ip.tcl
aldec
build_sw.sh
cadence
runall.tcl
mentor
synopsys
hdmi_rx
hdmi_tx
autotest_crc.v
bitec_hdmi_audio_gen.v
bitec_hdmi_tb.sv
tpg.v
Files
(Intel Quartus Prime Standard Edition)
(Intel Quartus Prime Standard Edition)
(Intel Quartus Prime Pro Edition)
(Intel Quartus Prime Standard Edition)
(Intel Quartus Prime Standard Edition)
(Intel Quartus Prime Pro Edition)
(Intel Quartus Prime Standard Edition)
(Intel Quartus Prime Pro Edition)
(Intel Quartus Prime Standard Edition)
(Intel Quartus Prime Standard Edition)
® ®
Arria 10 Devices
UG-20077 | 2017.11.06
software
tx_control_bsp
tx_control
tx_control_src
* Standard = Intel Quartus Prime Standard Edition
Pro = Intel Quartus Prime Pro Edition
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