Ports And Parameters - Intel Arria 10 User Manual

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
Table 278. Bit Values to Be Set
Disabling Reverse Serial Loopback Mode (Pre-CDR and Post-CDR)
To disable reverse-serial loopback mode, set the address bits to the following values,
by performing read-modify-write.
Table 279. Bit Values to Be Set
Related Information
Steps to Perform Dynamic Reconfiguration

6.13. Ports and Parameters

The reconfiguration interface is integrated in the Native PHY instance and the TX PLL
instances. Instantiate the Native PHY and the TX PLL IP cores in Qsys by clicking
Tools
specific parameter editor. To expose the reconfiguration interface ports, select the
Enable dynamic reconfiguration option when parameterizing the IP core.
You can share the reconfiguration interface among all the channels by turning on
Share reconfiguration interface when parameterizing the IP core. When this option
is enabled, the IP core presents a single reconfiguration interface for dynamic
reconfiguration of all channels. Address bits [9:0] provide the register address in the
reconfiguration space of the selected channel. The remaining address bits of the
reconfiguration address specify the selected logical channel. For example, if there are
four channels in the Native PHY IP instance,
address and
channels. For example, 2'b01 in
channel 1.
The following figure shows the signals available when the Native PHY IP core is
configured for four channels and the Share reconfiguration interface option is
enabled.
Address
0x137[7]
0x13C[7]
0x132[5:4]
0x142[4]
0x11D[0]
Address
0x137[7]
0x13C[7]
0x132[5:4]
0x142[4]
0x11D[0]
IP Catalog. You can define parameters for IP cores by using the IP core-
reconfig_address[11:10]
on page 516
reconfig_address[9:0]
are binary encoded to specify the four
reconfig_address[11:10]
Intel
Bit Values
1'b0
1'b1
2'b01
1'b0
1'b0
Bit Values
1'b0
1'b0
2'b00
1'b0
1'b0
specifies the
specifies logical
® ®
Arria 10 Transceiver PHY User Guide
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