Design Example - Intel Arria 10 User Manual

Figure 41. 24 Lanes Bonded Interlaken Link, RX Direction
To show more details, three different time segments are shown with different zoom level.
rx_enh_fifo_pempty
rx_enh_fifo_align_clr
rx_enh_fifo_align_val
Related Information
• Arria 10 Enhanced PCS Architecture
For more information about Enhanced PCS architecture
• Arria 10 PMA Architecture
For more information about PMA architecture
• Using PLLs and Clock Networks
For more information about implementing PLLs and clocks
• PLLs
PLL architecture and implementation details
• Resetting Transceiver Channels
Reset controller general information and implementation details
• Enhanced PCS Ports
For detailed information about the available ports in the Interlaken protocol

2.5.4. Design Example

Intel provides a PHY layer-only design example to help you integrate an Interlaken
PHY into your complete design.
The TX soft bonding logic is included in the design example. Intel recommends that
you integrate this module into your design.
The Interlaken Design Example is available on the Arria 10 Transceiver PHY Design
Examples Wiki page.
Note: The design examples on the Wiki page provide useful guidance for developing your
own designs, but they are not guaranteed by Intel. Use them with caution.
Related Information
Interlaken Design Example
® ®
Intel Arria 10 Transceiver PHY User Guide
106
rx_ready
Asserted
rx_clkout[0]
rx_digitalreset
24`hffffff 24`h000000
24`h00...
rx_ready
24`h000000 24`hff... 24`hffffff
rx_enh_blk_lock
24`h000000 24`hffffff
rx_enh_frame_lock
24`h000000 24`h0...
rx_enh_fifo_pfull[0]
rx_enh_fifo_pfull
24`h000000 24`h000000
24`hffffff 24`hffffff
24`h000000
24`h000000
24`h000000 24`h00...
rx_enh_fifi_rd_en
24`h000000 24`h000000
rx_enh_data_valid
24`h000000 24`h000000
rx_parallel_data
1536`h0100009c0100 1536`h0100009c0100009c0100009c0100009c0100009c0100009c0100009c01000
rx_control
240`h0441104411044 240`h044110441104404411044110441104411044110441104411044110441104411
on page 447
on page 349
on page 76
2. Implementing Protocols in Arria 10 Transceivers
Some Lanes pfull Signal Is Asserted
before All Lanes pempty is Deasserted;
RX Deskew Fails. Need to Realign
24`h000001
24`h000000
24`hfffffe
24`h000001
Assert align_clr
to Re-Align
on page 461
on page 398
on page 416
UG-01143 | 2018.06.15
All Lanes pfull Low and All
Lanes pempty Deasserted
RX Deskew Complete
24`h000000
24`hffffff
24`hffffff
24`hffffff
24`h00.. 24`h000000
24`hffffff 24`hffffff 24`h000000 24`h000000
24`h000000
24`hffffff
24`h00.. 24`hffffff
24`h000000 24`hffffff 24`h00.. 24`hffffff
24`h000000 24`hffffff 24`h00.. 24`hffffff
1536`h01000... 1536`h1e...
240`h044110... 240`h90a... 240`h826...
Start Reading Data
Based on FIFO Flags