Plls; Transmit Plls Spacing Guideline When Using Atx Plls And Fplls - Intel Arria 10 User Manual

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
• Using PLLs and Clock Networks
Information on how to use PLL IP to implement bonded and non-bonded
transceiver designs.

3.1. PLLs

Table 228. Transmit PLLs in Arria 10 Devices
Advanced Transmit (ATX) PLL
Fractional PLL (fPLL)
Clock Multiplier Unit (CMU) PLL or Channel PLL
Figure 169. Transmit PLL Recommendation Based on Data Rates
Related Information
Refer to Using PLL and Clock Networks section for guidelines and usage

3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs

ATX PLL-to-ATX PLL Spacing Guidelines
For ATX PLL VCO frequencies between 7.2 GHz and 11.4 GHz, when two ATX PLLs
operate at the same VCO frequency (within 100 MHz), they must be placed 7 ATX PLLs
apart (skip 6).
(50)
The CMU PLL or Channel PLL of channel 1 and channel 4 can be used as a transmit PLL or as a
clock data recovery (CDR) block. The channel PLL of all other channels (0, 2, 3, and 5) can
only be used as a CDR.
PLL Type
(50)
on page 398
Characteristics
• Best jitter performance
• LC tank based voltage controlled oscillator (VCO)
• Supports fractional synthesis mode (in cascade mode
only)
• Used for both bonded and non-bonded channel
configurations
• Ring oscillator based VCO
• Supports fractional synthesis mode
• Used for both bonded and non-bonded channel
configurations
• Ring oscillator based VCO
• Used as an additional clock source for non-bonded
applications
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Intel Arria
on page 398
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10 Transceiver PHY User Guide
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