10/100/1000 Ethernet (Hps) - Intel Arria 10 User Manual

5.9.2. 10/100/1000 Ethernet (HPS)

Figure 26.
Table 30.
FPGA Pin Number
H18
H19
F18
G17
E20
F20
G20
G21
F19
G19
F22
G22
H23
J23
K21
K20
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The development board supports an RJ-45 (
using an external Micrel KSZ9031RN PHY and the HPS EMAC function. The PHY-to-MAC
interface employs RGMII connection using four data lines at 250 Mbps each for a
connection speed of 1 Gbps.
The PHY interfaces to an RJ-45 model with internal magnetics that can be used for
driving copper lines with Ethernet traffic.
RGMII Interface between HPS (MAC) and PHY
RGMII
MAC
Ethernet (HPS) Pin Assignments
Shared I/O Bit
GPIO0_IO12
GPIO0_IO13
GPIO0_IO14
GPIO0_IO15
GPIO0_IO16
GPIO0_IO17
GPIO0_IO18
GPIO0_IO19
GPIO0_IO20
GPIO0_IO21
GPIO0_IO22
GPIO0_IO23
GPIO1_IO8
GPIO1_IO9
GPIO1_IO10
GPIO1_IO11
The Micrel KSZ9031RN PHY uses a multi-level POR bootstrap encoding scheme to
allow a small set of I/O pins (7) to set up a very large number of default settings
within the device. The related I/O pins have integrated pull-up or pull-down resistors
to configure the device.
10 SoC Development Kit User Guide
) 10/100/1000 base-T Ethernet
HPS_P3
Single-Port RGMII
Micrel KSZ9031RN
Schematic Signal Name
ENET_HPS_GTX_CLK
ENET_HPS_TX_EN
ENET_HPS_RX_CLK
ENET_HPS_RX_DV
ENET_HPS_TXD0
ENET_HPS_TXD1
ENET_HPS_RXD0
ENET_HPS_RXD1
ENET_HPS_TXD2
ENET_HPS_TXD3
ENET_HPS_RXD2
ENET_HPS_RXD3
ENETB_MDIO
ENETB_MDC
ENET_HPS_MDIO
ENET_HPS_MDC
5. Board Components
683227 | 2023.07.12
RJ-45
(HPS_P3)
Description
EMAC0 RGMII TX Clock
EMAC0 RGMII enable
EMAC0 RGMII RX Clock
EMAC0 RGMII RX DV flag
EMAC0 RGMII TXD0
EMAC0 RGMII TXD1
EMAC0 RGMII RXD0
EMAC0 RGMII RXD1
EMAC0 RGMII TXD2
EMAC0 RGMII TXD3
EMAC0 RGMII RXD2
EMAC0 RGMII RXD3
EMAC2 MDIO
EMAC2 MDIO
EMAC2 MDIO
EMAC2 MDIO
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