Recalibration After Transceiver Reference Clock Frequency Or Data Rate Change - Intel Arria 10 User Manual

7. Calibration
UG-01143 | 2018.06.15
7.4.1. Recalibration After Transceiver Reference Clock Frequency or Data
Rate Change
Figure 284. Recalibration Sequence when the Transceiver Reference Clock or Data Rate
Changes
7.4.1.1. User Recalibration
User recalibration requires access to the internal configuration bus and calibration
registers through the Avalon-MM reconfiguration interface. Follow the steps below to
perform a user recalibration.
1. Proceed to the next step if ATX PLL is not used in your application, otherwise
perform the ATX PLL calibration process:
a. Request access to the internal configuration bus by writing 0x2 to offset
address 0x0[7:0].
b. Wait for
capability register of PreSICE Avalon-MM interface control 0x280[2]=0x0.
c. Read-Modify-Write 0x1 to the offset address 0x100[0] of the ATX PLL.
d. Release the internal configuration bus to PreSICE to perform recalibration by
writing 0x1 to offset address 0x0[7:0].
e. Periodically check the
registers 0x280[1] to check
If you are recalibrating your ATX PLL and have adjacent ATX PLL used on the same
side of the device, follow the ATX PLL-to-ATX PLL spacing guideline as stated in the
"Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter.
2. Proceed to the next step if fPLL is not used in your application, otherwise perform
the fPLL user recalibration process:
ATX PLL Calibration
fPLL Calibration
PMA RX
Calibration (1)
PMA TX
Calibration (2)
Calibration
Done
Note:
(1) If you are using the CDR/CMU PLL, you need to trigger RX PMA recalibration.
(2) If you are using the CMU PLL, you need to trigger RX PMA recalibration
followed by a TX PMA recalibration.
reconfig_waitrequest
*cal_busy
to deassert (logic low), or wait until
output signals or read the capability
status until calibration is complete.
*cal_busy
®
Intel Arria
®
10 Transceiver PHY User Guide
579