Transmitter Datapath - Intel Arria 10 User Manual

Figure 252. Standard PCS Datapath Diagram

5.3.1. Transmitter Datapath

5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe Gen3 PCS)
The TX FIFO interfaces between the transmitter PCS and the FPGA fabric and ensures
reliable transfer of data and status signals. It compensates for the phase difference
between the FPGA fabric clock and
FIFO has a depth of 8 and operates in low latency mode, register mode, and fast
register mode.
Figure 253. TX FIFO Block Diagram
Datapath to Byte Serializer,
8B/10B Encoder,
or Serializer
You can control the write port using
tx_clkout
channels. The TX FIFO is shared with PCIe Gen3 and Enhanced PCS data paths.
® ®
Intel Arria 10 Transceiver PHY User Guide
480
Transmitter PMA
tx_clkout
tx_pma_div_clkout
Receiver PMA
Parallel Clock
(Recovered) rx_clkout
tx_clkout
Parallel Clock
(From Clock
Divider)
Parallel Clock
Serial Clock
Parallel and Serial Clock
tx_clkout
signal for a single channel and
5. Arria 10 Transceiver PHY Architecture
PRBS
Generator
/2, /4
/2, /4
PRBS
Verifier
rx_pma_div_clkout
Clock Generation Block (CGB)
Clock Divider
Parallel and Serial Clock
(the low-speed parallel clock). The TX
tx_clkout
TX
FIFO
rd_clk wr_clk
or
tx_clkout tx_coreclkin
tx_coreclkin
UG-01143 | 2018.06.15
Transmitter Standard PCS
FPGA
Fabric
tx_coreclkin
tx_clkout
Receiver Standard PCS
rx_coreclkin
rx_clkout or
tx_clkout
ATX PLL
CMU PLL
fPLL
Serial Clock
Datapath from FPGA Fabric
or PIPE Interface
tx_coreclkin
. Use the
when using multiple