Arria 10 Sx Device Package Details - Intel Arria 10 User Manual

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1. Arria 10 Transceiver PHY Overview
UG-01143 | 2018.06.15
Figure 10. Arria 10 SX Device with 12 Transceiver Channels and One Hard IP Block
CH5
CH4
CH3
CH2
CH1
CH0
Note:
(1) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities.
Arria 10 SX device with 12 transceiver channels and one Hard IP block.
Figure 11. Arria 10 SX Device with Six Transceiver Channels and One Hard IP Block
CH5
CH4
CH3
CH2
CH1
CH0
Note:
(1) Only CH5 and CH4 support PCIe Hard IP block with Configuration via Protocol (CvP) capabilities.
(2) These devices have transceivers only on the left hand side of the device.
Legend:
PCIe Gen1 - Gen3 Hard IP block with Configuration via Protocol (CvP) capabilities.
Arria 10 SX device with six transceiver channels and one PCIe Hard IP block.
Related Information
• IntelArria 10 Avalon-ST Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-MM Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide
• IntelArria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide

1.1.5. Arria 10 SX Device Package Details

The following tables list package sizes, available transceiver channels, and PCI Express
Hard IP blocks for Arria 10 SX devices.
GXBL1D GXBL1D
Transceiver
Bank
GXBL1C GXBL1C
Transceiver
Bank
GXBL1C
SX 048 EF29
SX 032 EF29
Transceiver Transceiver
PCIe
SX 032 EF27
Bank Bank Gen1 - Gen3
SX 027 EF29
Hard IP
SX 027 EF27
(with CvP)
SX 022 EF29
SX 022 EF27
SX 016 EF29
Transceiver Transceiver
SX 016 EF27
Bank Bank
PCIe Hard IP (1)
SX 022 CU19
Transceiver Transceiver
SX 016 CU19
Bank Bank
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10 Transceiver PHY User Guide
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