Preset Mappings To Tx De-Emphasis - Intel Arria 10 User Manual

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Port
pcie_sw[1:0]
pcie_sw_done[1:0]
Related Information
Using the Arria 10 Transceiver Native PHY IP Core

2.7.11. Preset Mappings to TX De-emphasis

Table 194. Arria 10 Preset Mappings to TX De-emphasis
Preset
0
1
2
3
4
5
6
7
8
9
10
The
pipe_g3_txdeemph
emphasis during equalization. The 18 bits specify the following coefficients:
[5:0]: C
-1
[11:6]: C
[17:12]: C
Direction Clock Domain
Input Asynchronous
Output Asynchronous
C
+1
001111
001010
001100
001000
000000
000000
000000
001100
001000
000000
010110
port is used to select the link partner's transmitter de-
0
+1
Description
For Gen3x2,x4,x8 use the
tx_bonding_clocks
the ATX PLL to connect to the
the Native PHY.
2-bit rate switch control input used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen 2x2,x4,x8 connect the
PHY to this port.
For Gen3x2,x4,x8 use the
pipe_sw
drive this port.
2-bit rate switch status output used for PCIe protocol
implementation.
For Gen1, this port is N/A.
For Gen2x2, x4, x8 connect the
ATX PLL to input of Native PHY .
pipe_sw_done
For Gen3x2, x4, x8
pcie_sw_done
input of Native PHY.
pipe_sw_done
on page 45
C
0
101101
110010
110000
110100
111100
110110
110100
101010
101100
110010
100110
®
Intel Arria
output from
input of
tx_bonding_clocks
output from Native
pipe_sw
output from Native PHY to
output from
pcie_sw_done
output from ATX PLL to
C
-1
000000
000000
000000
000000
000000
000110
001000
000110
001000
001010
000000
®
10 Transceiver PHY User Guide
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