Xaui Phy Pma Channel Controller Interface; Xaui Phy Optional Pma Control And Status Interface - Intel Arria 10 User Manual

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
2.6.6.9.4. XAUI PHY Clocks, Reset, and Powerdown Interfaces
Figure 89. Clock Inputs and Outputs for IP Core with Soft PCS
phy_mgmt_clk
pll_ref_clk
xgmii_tx_clk
xgmii_rx_clk
Table 174. Clock and Reset Signals
Signal Name
pll_ref_clk

2.6.6.9.5. XAUI PHY PMA Channel Controller Interface

Table 175. PMA Channel Controller Signals
Signal Name
rx_recovered_clk[3:0]
rx_ready
tx_ready
pll_cal_busy_i

2.6.6.9.6. XAUI PHY Optional PMA Control and Status Interface

Use the Avalon-MM PHY Management interface to read the state of the optional PMA
control and status signals available in the XAUI PHY IP core registers. In some cases
you may need to know the instantaneous value of a signal to ensure correct
functioning of the XAUI PHY. In such cases, you can include the required signal in the
top-level module of your XAUI PHY IP core.
Table 176. Optional Control and Status Signals—Soft IP Implementation
Signal Name
rx_channelaligned
rx_disperr[7:0]
XAUI Soft IP Core
Soft PCS
pma_tx_clkout
pma_pll_inclk
pma_rx_clkout
sysclk
Direction
Input This is a 156.25 MHz reference clock that is used by the CDR
logic.
Direction
Output This is the RX clock, which is recovered from the received data
stream.
Output Indicates PMA RX has exited the reset state and the transceiver
can receive data. Synchronous to
Output Indicates PMA TX has exited the reset state and the transceiver
can transmit data. Synchronous to
Input Indicates the PLL calibration status.
Direction
Output
Output
pll_ref_clk
PMA
tx_clkout
rx_recovered_clk
Description
Description
mgmt_clk
mgmt_clk
Description
When asserted, indicates that all 4 RX channels are
aligned. Synchronous to
mgmt_clk
asserted when the RX lanes are fully aligned and ready
to receive data.
Received 10-bit code or data group has a disparity
error. It is paired with
rx_errdetect
asserted when a disparity error occurs. The
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Intel Arria 10 Transceiver PHY User Guide
4
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4 x 3.125 Gbps serial
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.
. This signal is
which is also
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