Hps Shared I/O - Intel Arria 10 User Manual

5.9.5. HPS Shared I/O

Table 37.
Pin Number
D18
E18
C19
D19
E17
F17
C17
C18
D21
D20
E21
E22
H18
H19
F18
G17
E20
F20
G20
G21
F19
G19
F22
G22
K18
L19
H22
H21
J21
J20
J18
J19
H23
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Intel Arria
88
Arrow.com.
Downloaded from
HPS Shared I/O
Shared I/O Bit
GPIO0_IO0 USB_CLK
GPIO0_IO1 USB_STP
GPIO0_IO2 USB_DIR
GPIO0_IO3 USB_DATA0
GPIO0_IO4 USB_DATA1
GPIO0_IO5 USB_NXT
GPIO0_IO6 USB_DATA2
GPIO0_IO7 USB_DATA3
GPIO0_IO8 USB_DATA4
GPIO0_IO9 USB_DATA5
GPIO0_IO10 USB_DATA6
GPIO0_IO11 USB_DATA7
GPIO0_IO12 ENET_HPS_GTX_CLK
GPIO0_IO13 ENET_HPS_TX_EN
GPIO0_IO14 ENET_HPS_RX_CLK
GPIO0_IO15 ENET_HPS_RX_DV
GPIO0_IO16 ENET_HPS_TXD0
GPIO0_IO17 ENET_HPS_TXD1
GPIO0_IO18 ENET_HPS_RXD0
GPIO0_IO19 ENET_HPS_RXD1
GPIO0_IO20 ENET_HPS_TXD2
GPIO0_IO21 ENET_HPS_TXD3
GPIO0_IO22 ENET_HPS_RXD2
GPIO0_IO23 ENET_HPS_RXD3
GPIO1_IO0 SPIM1_CLK
GPIO1_IO1 SPIM1_MOSI
GPIO1_IO2 SPIM1_MISO
GPIO1_IO3 SPIM1_SS0_N
GPIO1_IO4 SPIM1_SS1_N
GPIO1_IO5 A10SH_GPIO0
GPIO1_IO6 UARTA_TX
GPIO1_IO7 UARTA_RX
GPIO1_IO8 ENETB_MDIO
10 SoC Development Kit User Guide
Schematic Signal Name
USB2.0 Clock
USB2.0 Stop bit
USB2.0 direction bit
USB2.0 data line 0
USB2.0 data line 1
USB2.0 NXT flag
USB2.0 data line 2
USB2.0 data line 3
USB2.0 data line 4
USB2.0 data line 5
USB2.0 data line 6
USB2.0 data line 7
EMAC0 RGMII TX Clock
EMAC0 RGMII
EMAC0 RGMII RX Clock
EMAC0 RGMII RX DV flag
EMAC0 RGMII TXD0
EMAC0 RGMII TXD1
EMAC0 RGMII RXD0
EMAC0 RGMII RXD1
EMAC0 RGMII TXD2
EMAC0 RGMII TXD3
EMAC0 RGMII RXD2
EMAC0 RGMII RXD3
MAXV IO SPI Clock
MAXV IO SPI Master Output/Slave input
MAXV IO SPI Slave Input/Master output
MAXV IO SPI chip select 0
MAXV IO SPI Chip Select 1
MAXV_GPIO0
UART port 1 TX
UART PORT 1 RX
EMAC2 MDIO
5. Board Components
683227 | 2023.07.12
Description
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