Multiple Reconfiguration Profiles - Intel Arria 10 User Manual

6. Reconfiguration Interface and Dynamic Reconfiguration
UG-01143 | 2018.06.15
• Analog Parameter Settings
• Arria 10 Transceiver Register Map

6.4. Multiple Reconfiguration Profiles

You can optionally enable multiple configurations or profiles in the same Native PHY IP
or ATX PLL IP core Parameter Editor (or both) for performing dynamic reconfiguration.
This allows the IP Parameter Editor to create, store, and analyze the parameter
settings for multiple configurations or profiles.
When you enable the multiple reconfiguration profiles feature, the Native PHY IP Core,
ATX PLL IP core, or both can generate configuration files for all the profiles in the
format desired (SystemVerilog package, MIF, or C header file). The configuration files
are located in the
type>_a10_<quartus version>\synth\reconfig
with the configuration profile index added to the filename. For example, the
configuration file for Profile 0 is stored as
Prime Timing Analyzer Timing Analyzer includes the necessary timing paths for all the
configurations based on initial and target profiles. You can also generate reduced
configuration files that contain only the attributes that differ between the multiple
configured profiles. You can create up to eight reconfiguration profiles (Profile 0 to
Profile 7) at a time for each instance of the Native PHY/ATX PLL IP core.
You can optionally allow the Native PHY IP core to include PMA Analog settings in the
configuration files by enabling the feature Include PMA Analog settings in
configuration files in the Dynamic Reconfiguration tab of the Transceiver Native
PHY IP Parameter Editor. This feature is disabled by default. Enabling this feature adds
the PMA analog settings specified in the Analog PMA settings (Optional) tab of the
Native PHY IP Parameter Editor to the configuration files. Even with this option
enabled in the Native PHY IP Parameter Editor, you must still specify QSF assignments
for your analog settings when compiling your static design. The analog settings
selected in the Native PHY IP Parameter Editor are used only to include these settings
and their dependent settings in the selected configuration files. Refer to the Analog
Parameter Settings chapter for details about QSF assignments for the analog settings.
Refer to Steps to Perform Dynamic Reconfiguration for a complete list of steps to
perform dynamic reconfiguration using the IP guided reconfiguration flow with multiple
reconfiguration profiles enabled.
The Quartus Prime Timing Analyzer only includes the necessary PCS timing paths for
all the profiles. To perform a PMA reconfiguration such as TX PLL switching, CGB
divider switching, or reference clock switching, you must use the flow described in
Steps to Perform Dynamic Reconfiguration. Refer to Timing Closure Recommendations
for more details about enabling multiple profiles and running timing analyses.
You can use the multiple reconfiguration profiles feature without using the embedded
reconfiguration streamer feature. When using the multiple reconfiguration profiles
feature by itself, you must write the user logic to reconfigure all the entries that are
different between the profiles while moving from one profile to another.
on page 585
<IP instance name>\altera_xcvr_<IP
subfolder of the IP instance
<filename_CFG0.sv>
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Intel Arria 10 Transceiver PHY User Guide
. The Intel Quartus
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