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A. Additional Information
A.1. Document Revision History for the Intel Arria 10 SoC
Development Kit User Guide
Document
Version
2023.07.12
Table 56.
August 2018
September 2017
August 2017
December 2016
December 2016
July 2016
June 2016
May 2016
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Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
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Arrow.com.
Downloaded from
•
Retitled the document from Arria 10 SoC Development Kit User Guide to Intel Arria 10 SoC
Development Kit User Guide.
•
Minor text edits.
Intel Arria 10 SoC Development Kit User Guide Revision History
Date
Version
2018.08.09
2017.09.05
2017.08.08
2016.12.29
2016.12.22
2016.07.29
2016.06.30
2016.05.26
Changes
Changes
Updated
Memory
on page 105. HPS-EMIF only supports DDR3 and DDR4
while the FPGA EMIF supports the rest of the protocols.
•
Updated Dedicated I/O Pin Assignments table in
Interface
on page 115
•
Updated the name of the battery used in
page 91
Added a Caution note to
Handling the Board
•
Updated FMCA LVDS Signal I/O Assignments Table in
Updates:
•
Table added to
General User Input/Output
Updated:
•
Board Inspection
on page 10
•
Installing the USB-Blaster Driver
•
Default Switch and Jumper Settings
•
Version Selector
on page 22
•
The System Info Tab
on page 26
•
System Controller Configuration
•
FPGA and I/O MUX CPLD Programming over On-Board USB-Blaster II
on page 61
•
FPGA-I/O MAX V Interface
on page 93
Added:
•
Version Selector
on page 22
•
The EEPROM Tab
on page 43
Updated:
•
Installing the USB-Blaster Driver
•
Board Test System GUI Screenshots
Updated:
HPS Boot Flash
Real-Time Clock (HPS)
on
on page 9
FMC
on page 75
on page 67
on page 13
on page 16
on page 60
on page 13
continued...
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9001:2015
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