Fpga General I/O Configuration - Intel Arria 10 User Manual

5. Board Components
683227 | 2023.07.12

5.9.11. FPGA General I/O Configuration

5.9.11.1. FPGA-I/O MAX V Interface
Table 42.
Bank
3E
3E
3E
3E
3E
3E
3E
3E
3E
3E
3E
3E
3E
3E
3E
3E
2I
2I
2I
2I
2I
2I
2I
2I
2I
2I
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Thirteen FPGA I/O pairs (FPGAIO_NP signals) are connected to FPGA I/O MAX V CPLD
for Ethernet, FPGA User IOs, Display port, and SDI applications support.
I/O Assignments of FPGA I/O Pairs
Pin Number
M2
M1
N4
N3
R3
R2
N2
N1
R1
P1
P4
P3
P6
P5
T5
R5
AR22
AR23
AL22
AM22
AP21
AR21
AN22
AN21
AL20
AM21
The figure below illustrates the signal connections between two MAX Vs and FPGA.
Schematic Signal Name
FPGAIO9_N
FPGAIO9_P
FPGAIO8_N
FPGAIO8_P
FPGAIO7_N
FPGAIO7_P
FPGAIO6_N
FPGAIO6_P
FPGAIO5_N
FPGAIO5_P
FPGAIO4_N
FPGAIO4_P
FPGAIO3_N
FPGAIO3_P
FPGAIO2_N
FPGAIO2_P
FPGAIO_N
FPGAIO_P
FPGAIO12_N
FPGAIO12_P
FPGAIO11_N
FPGAIO11_P
FPGAIO10_N
FPGAIO10_P
FPGAIO1_N
FPGAIO1_P
® ®
Intel Arria 10 SoC Development Kit User Guide
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