Other Protocols; Using The "Basic (Enhanced Pcs)" And "Basic With Kr Fec" Configurations Of Enhanced Pcs - Intel Arria 10 User Manual

2. Implementing Protocols in Arria 10 Transceivers
UG-01143 | 2018.06.15
Enable control and status registers
Enable prbs soft accumulators
Configuration file prefix
Generate SystemVerilog package file
Generate C header file
Generate MIF (Memory Initialization File)
Table 210. Generation Options
Generate parameter documentation file

2.9. Other Protocols

2.9.1. Using the "Basic (Enhanced PCS)" and "Basic with KR FEC"
Configurations of Enhanced PCS
You can use Arria 10 transceivers to configure the Enhanced PCS to support other 10G
or 10G-like protocols. The Basic (Enhanced PCS) transceiver configuration rule allows
access to the Enhanced PCS with full user control over the transceiver interfaces,
parameters, and ports.
You can configure the transceivers for Basic functionality using the Native PHY IP
Basic (Enhanced PCS) transceiver configuration rule.
Basic with KR FEC is a KR FEC sublayer support with a low latency physical coding
sublayer (PCS). The KR FEC sublayer increases the bit error rate (BER) performance of
a link. This mode can run up to a data rate of 25.8 Gbps. Use this configuration to
implement applications with low latency or low BER requirements or applications such
as 10 Gbps, 40 Gbps or 100 Gbps Ethernet over backplane (10GBASE-KR protocol).
The Forward Error Correction (FEC) function is defined in Clause 74 of IEEE
802.3ap-2007. FEC provides an error detection and correction mechanism that allows
noisy channels to achieve the Ethernet-mandated Bit Error Rate (BER) of 10
FEC sublayer provides additional link margin by compensating for variations in
manufacturing and environmental conditions. To distinguish it from other FEC
mechanisms (for example, Optical Transport Network FEC), FEC as defined in Clause
74 of IEEE 802.3ap-2007 is called KR FEC.
Note: This configuration supports the FIFO in phase compensation and register modes, and
KR FEC PCS blocks. You can implement all other required logic for your specific
application, such as standard or proprietary protocol multi-channel alignment, either
in the FPGA fabric in soft IP or use Intel's 10GBASE-KR PHY IP core product as full
solutions in the FPGA.
Parameter
Parameter
Value
Off
Off
altera_xcvr_native_a10
Off
Off
Off
Value
On
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Intel Arria 10 Transceiver PHY User Guide
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