Fpll - Intel Arria 10 User Manual

3. PLLs and Clock Networks
UG-01143 | 2018.06.15
Port
pcie_sw[1:0]
pcie_sw_done[1:0]
atx_to_fpll_cascade_clk
ext_lock_detect_clklow
ext_lock_detect_fref
Related Information
• Calibration
• Avalon Interface Specifications
The ports related to reconfiguration are compliant with the Avalon specification.
Refer to the Avalon specification for more details about these ports.
• Intel Arria 10 Device Datasheet
Refer to the Intel Arria 10 Device Datasheet for more details about the PLL
output frequency range.
• Reconfiguration Interface and Dynamic Reconfiguration
• Reconfiguring Channel and PLL Blocks
• Steps to Perform Dynamic Reconfiguration
• Intel Arria 10 device fPLL reports an unlocked condition

3.1.3. fPLL

There are two fPLLs in each transceiver bank with six channels (one located at the top
and the other at the bottom of the bank). Transceiver banks with three channels have
only one fPLL.
Figure 171. fPLL Block Diagram
Output of Another PLL with PLL Cascading
(55)
The fPLL and
fref
detection logic.
Direction
Input
Output
Output
(55)
Output
(55)
Output
on page 29
Refclk
Multiplexer
Dedicated Reference Clock Pin Input
Reference
Reference Clock Network
Clock
Receiver Input Pin
Global Clock or Core Clock
signals should only be used with the Intel external soft lock
clklow
Clock Domain
Asynchronous 2-bit rate switch control input used for
PCIe protocol implementation.
Asynchronous 2-bit rate switch status output used for
PCIe protocol implementation.
N/A The ATX PLL output clock is used to
drive fPLL reference clock input (only
available in SDI_cascade or
OTN_cascade protocol mode).
N/A
Clklow
detection. It can be exposed by
selecting the Enable clklow and fref
port
N/A Fref output for external lock detection.
It can be exposed by selecting the
Enable clklow and fref port.
on page 503
on page 516
Up Charge
refclk
N Counter PFD Pump and
Loop Filter
Down
fbclk
Intel
Description
output for external lock
on page 502
L Counter
/1, 2, 4, 8
M Counter
VCO /2
Delta Sigma
Modulator
/2 C Counter
® ®
Arria 10 Transceiver PHY User Guide
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