Page 1: User Guide
® ® Intel Arria 10 Transceiver PHY User Guide ® ® Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe UG-01143 | 2018.06.15 Send Feedback Latest document on the web: HTML...
Page 2: Table Of Contents
1.1.1. Arria 10 GX Device Transceiver Layout............10 1.1.2. Arria 10 GT Device Transceiver Layout............15 1.1.3. Arria 10 GX and GT Device Package Details ..........17 1.1.4. Arria 10 SX Device Transceiver Layout............17 1.1.5. Arria 10 SX Device Package Details............19 1.2.
Page 3 2.7.2. Supported PIPE Features................. 231 2.7.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes....240 2.7.4. How to Implement PCI Express (PIPE) in Arria 10 Transceivers....246 2.7.5. Native PHY IP Parameter Settings for PIPE ..........248 2.7.6.
Page 4 4.5.1. User-Coded Reset Controller Signals............441 4.6. Combining Status or PLL Lock Signals ..............442 4.7. Timing Constraints for Bonded PCS and PMA Channels..........443 4.8. Resetting Transceiver Channels Revision History............. 445 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 5 5.4.1. Transmitter Datapath................496 5.4.2. Receiver Datapath.................. 497 5.4.3. PIPE Interface..................498 5.5. Intel Arria 10 Transceiver PHY Architecture Revision History........499 6. Reconfiguration Interface and Dynamic Reconfiguration .......... 502 6.1. Reconfiguring Channel and PLL Blocks..............503 6.2. Interacting with the Reconfiguration Interface............503 6.2.1.
Page 6 8.7.4. XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP........601 8.7.5. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T......602 8.7.6. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T......602 8.7.7. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP..... 603 8.7.8. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP..... 604 8.8. Transmitter VOD Settings..................604 8.8.1. XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL..........604 8.9. Dedicated Reference Clock Settings..............605 8.9.1. XCVR_A10_REFCLK_TERM_TRISTATE............605 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 7 Contents 8.9.2. XCVR_A10_TX_XTX_PATH_ANALOG_MODE..........606 8.10. Unused Transceiver RX Channels Settings............606 8.11. Analog Parameter Settings Revision History............606 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 8: Arria ® 10 Transceiver Phy Overview
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 9: Device Transceiver Layout
Figure 1. Arria 10 FPGA Architecture Block Diagram The transceiver channels are placed on the left side periphery in most Arria 10 devices. For larger Arria 10 devices, additional transceiver channels are placed on the right side periphery. For GT device variants, the maximum transceiver data rates are specified for (-1) transceiver speed grade.
Page 10: Arria 10 Gx Device Transceiver Layout
UG-01143 | 2018.06.15 1.1.1. Arria 10 GX Device Transceiver Layout The largest Arria 10 GX device includes 96 transceiver channels. A column array of eight transceiver banks on the left and the right side periphery of the device is shown in the following figure.
Page 11 PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities. PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities. Arria 10 GX device with 96 transceiver channels and four PCIe Hard IP blocks. ®...
Page 12 ® 1. Arria 10 Transceiver PHY Overview UG-01143 | 2018.06.15 Figure 3. Arria 10 GX Devices with 72 and 48 Transceiver Channels and Four PCIe Hard IP Blocks. GX 115 SF45 GX 090 SF45 Transceiver Transceiver Transceiver GXBL1H GXBR4H Bank...
Page 13 PCIe Gen1 - Gen3 Hard IP blocks with Configuration via Protocol (CvP) capabilities. PCIe Gen1 - Gen3 Hard IP blocks without Configuration via Protocol (CvP) capabilities. Arria 10 GX device with 66 transceiver channels and three PCIe Hard IP blocks. ®...
Page 14 ® 1. Arria 10 Transceiver PHY Overview UG-01143 | 2018.06.15 Figure 5. Arria 10 GX Devices with 48, 36, and 24 Transceiver Channels and Two PCIe Hard IP Blocks GX 115 NF40 Transceiver Transceiver GX 090 NF40 GXBL1J GXBL1J Bank...
Page 15: Arria 10 Gt Device Transceiver Layout
IntelArria 10 Avalon-ST Interface with SR-IOV PCIe Solutions User Guide 1.1.2. Arria 10 GT Device Transceiver Layout The Arria 10 GT device has 72 transceiver channels and four PCI Express Hard IP blocks. A total of 6 GT transceiver channels that can support data rates up to 25.8 Gbps.
Page 16 If you're using GT transceivers in bank GXBL1E, then the adjacent PCIe Hard IP block cannot be used. Figure 8. Arria 10 GT Device with 72 Transceiver Channels and Four PCIe Hard IP Blocks GT 115 SF45 Transceiver...
Page 17: Arria 10 Gx And Gt Device Package Details
1.1.3. Arria 10 GX and GT Device Package Details The following tables list package sizes, available transceiver channels, and PCI Express Hard IP blocks for Arria 10 GX and GT devices. Table 3. Package Details for GX Devices with Transceivers and Hard IP Blocks Located on the Left Side Periphery of the Device •...
Page 18 For more information about PCIe Hard IP transceiver placements, refer to Related Information at the end of this section. Figure 9. Arria 10 SX Device with 48, 36, and 24 Transceiver Channels and Two Hard IP Blocks SX 066 NF40...
Page 19: Arria 10 Sx Device Package Details
(2) These devices have transceivers only on the left hand side of the device. Legend: PCIe Gen1 - Gen3 Hard IP block with Configuration via Protocol (CvP) capabilities. Arria 10 SX device with six transceiver channels and one PCIe Hard IP block. Related Information •...
Page 20: Transceiver Phy Architecture Overview
The figures below show the transceiver bank architecture with the phase locked loop (PLL) and clock generation block (CGB) resources available in each bank. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 21 Local CGB0 PLL0 Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 22 (CDR Only) PLL0 Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 23 GX Channel GT/GX Channel Note: This figure is a high level overview of the transceiver bank architecture. For details about the available clock networks refer to the PLLs and Clock Networks chapter. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 24 PLLs. The master and local clock generation blocks (CGBs) provide the necessary high speed serial and low speed parallel clocks to drive the non-bonded and bonded channels in the transceiver bank. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 25: Phy Layer Transceiver Components
PCS Direct Notes: (1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable. Arria 10 GX transceiver channels have three types of PCS blocks that together support continuous data rates between 1.0 Gbps and 17.4 Gbps. ® ®...
Page 26 1.0 Gbps to 17.4 Gbps. Applies when operating in reduced power modes. For standard power modes, the Enhanced PCS minimum data rate is 1600 Mbps. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 27 The Enhanced PCS must be configured in Basic low latency mode to support data rate range from 17.4 Gbps to 25.8 Gbps. Applies when operating in reduced power modes. For standard power modes, the Enhanced PCS minimum data rate is 1600 Mbps. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 28: Transceiver Phase-Locked Loops
10 Transceiver PHY Overview UG-01143 | 2018.06.15 Related Information IntelArria 10 Device Datasheet 1.2.3. Transceiver Phase-Locked Loops Each transceiver channel in Arria 10 devices has direct access to three types of high performance PLLs: • Advanced Transmit (ATX) PLL •...
Page 29: Clock Generation Block (Cgb)
• CMU PLL IP Core on page 370 For information on implementing CMU PLL IP. 1.2.4. Clock Generation Block (CGB) In Arria 10 devices, there are two types of clock generation blocks (CGBs): • Master CGB • Local CGB Transceiver banks with six transceiver channels have two master CGBs. Master CGB1 is located at the top of the transceiver bank and master CGB0 is located at the bottom of the transceiver bank.
Page 30: Intel Arria 10 Transceiver Phy Overview Revision History
Changed the Data Rates Supported for GT channel Standard PCS and PCIe Gen3 PCS types in the "PCS Types and Data Rates Supported by GT Channel Configurations" table. • Added a related link to the Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines in the "Calibration" section. 2014.08.15 Made the following changes: •...
Page 31 Document Changes Version • Updated figure "Arria 10 SX Device with 48,36, and 24 Transceiver Channels and Two PCIe Hard IP Blocks. • Updated figure "Arria 10 SX Devices with Six Transceiver Channels and One PCIe Hard IP Block" to add a clarification about PCIe Hard IP.
Page 32: Implementing Protocols In Arria 10 Transceivers
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 33: Transceiver Design Flow
Figure 19. Transceiver Design Flow Note: The design examples on the Intel FPGA wiki page provide useful guidance for developing your own design. However, the content on the Intel FPGA wiki page is not guaranteed by Intel. Select PHY IP Core...
Page 34 1. Open the Quartus Prime software. 2. Click Tools IP Catalog. 3. At the top of the IP Catalog window, select Arria 10 device family 4. In IP Catalog, under Library Interface Protocols, select the appropriate PHY IP and then click Add.
Page 35: Configure The Phy Ip Core
Refer to the appropriate protocol's section for selecting valid parameters for each protocol. Related Information • Using the Arria 10 Transceiver Native PHY IP Core on page 45 For information on Native PHY IP. ®...
Page 36: Generate The Phy Ip Core
IP Core File Locations on page 91 For more information about IP core file structure 2.2.4. Select the PLL IP Core Arria 10 devices have three types of PLL IP cores: • Advanced Transmit (ATX) PLL IP core. • Fractional PLL (fPLL) IP core.
Page 37 To instantiate a PLL IP: 1. Open the Quartus Prime software. 2. Click Tools IP Catalog. 3. At the top of the IP Catalog window, select Arria 10 device family 4. In IP Catalog, under Library Basic Functions Clocks, PLLs, and Resets...
Page 38: Configure The Pll Ip Core
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 21. Arria 10 Transceiver PLL Types Related Information PLLs on page 349 2.2.5. Configure the PLL IP Core Understand the available PLLs, clock networks, and the supported clocking configurations. Configure the PLL IP to achieve the adequate data rate for your design.
Page 39: Generate The Pll Ip Core
IP Core File Locations on page 91 For more information about IP core file structure 2.2.7. Reset Controller There are two methods to reset the transceivers in Arria 10 devices: • Use the Transceiver PHY Reset Controller. • Create your own reset controller that follows the recommended reset sequence.
Page 40: Connect The Phy Ip To The Pll Ip Core And Reset Controller
Standard PCS Ports on page 86 • Resetting Transceiver Channels on page 416 • Using the Arria 10 Transceiver Native PHY IP Core on page 45 • PLLs and Clock Networks on page 347 2.2.10. Connect Datapath Connect the transceiver PHY layer design to the Media Access Controller (MAC) IP core or to a data generator / analyzer or a frame generator / analyzer.
Page 41: Compile The Design
IP for PCI (11) Express continued... For more information about Transceiver Configuration Rules, refer to Using the Intel Arria 10Transceiver Native PHY IP Core section. (10) For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver Native PHY IP Core section.
Page 42 User created Enhanced (Standard PCS) continued... For more information about Transceiver Configuration Rules, refer to Using the Intel Arria 10Transceiver Native PHY IP Core section. (10) For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver Native PHY IP Core section.
Page 43 SONET/SDH OC-96 via OIF SFI-5.1s (Standard PCS) continued... For more information about Transceiver Configuration Rules, refer to Using the Intel Arria 10Transceiver Native PHY IP Core section. (10) For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver Native PHY IP Core section.
Page 44 (Manual) Mode continued... For more information about Transceiver Configuration Rules, refer to Using the Intel Arria 10Transceiver Native PHY IP Core section. (10) For more information about Protocol Presets, refer to Using the Intel Arria 10Transceiver Native PHY IP Core section.
Page 45: Using The Arria 10 Transceiver Native Phy Ip Core
AN745: Design Guidelines for DisplayPort and HDMI Interfaces 2.4. Using the Arria 10 Transceiver Native PHY IP Core This section describes the use of the Intel-provided Arria 10 Transceiver Native PHY IP core. This Native PHY IP core provides direct access to Arria 10 transceiver PHY features.
Page 46 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 preset that matches your protocol configuration as a starting point. Presets are PHY IP configuration settings for various protocols that are stored in the IP Parameter Editor. Presets are explained in detail in the Presets section below.
Page 47 Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of Enhanced PCS on page 289 • Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard on page 300 • Design Considerations for Implementing Arria 10 GT Channels on page 319 • PMA Parameters on page 51 • Presets on page 48 •...
Page 48: Presets
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.4.1. Presets You can select preset settings for the Native PHY IP core defined for each protocol. Use presets as a starting point to specify parameters for your specific protocol or application.
Page 49 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value Description Note: This option is only used for GUI rule validation. Use Quartus Prime Setting File (.qsf) assignments to set this parameter in your static design. Transceiver User Selection Specifies the valid configuration rules for the transceiver.
Page 50 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value Description Enable datapath and On/Off When you turn this option on, you can preconfigure and interface dynamically switch between the Standard PCS, Enhanced PCS, and reconfiguration PCS direct datapaths.
Page 51: Pma Parameters
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Transceiver Configuration Setting Description 10GBASE-R 1588 Enforces rules required by the 10GBASE-R protocol with 1588 enabled. 10GBASE-R w/KR FEC Enforces rules required by the 10GBASE-R protocol with KR FEC block enabled.
Page 52 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value Description network. The master CGB generates both the high and low speed clocks. The master channel generates the PCS control signals and distributes to other channels through a control plane block.
Page 53 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value Description Enable On/Off Enables the optional output clock. This tx_pma_iqtxrx_clkout tx_pma_iqtxrx_clkout port clock can be used to cascade the TX PMA output clock to the input of a PLL.
Page 54 Refer to the Decision Feedback Equalization (DFE) on page 454 section in the Arria 10 Transceiver PHY Architecture chapter for more details about DFE. Refer to How to Enable CTLE and DFE page 456 for more details on supported adaptation modes.
Page 55: Enhanced Pcs Parameters
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameters Value Description Enable On/Off Enables the control input port. Use this port rx_pma_qpipulldn rx_pma_qpipulldn port only for QPI applications. (QPI) Enable On/Off Enables the optional status output port. rx_is_lockedtodata...
Page 56 Enhanced PCS are bypassed to provide the lowest latency path from the PMA through the Enhanced PCS. When enabled, this mode is applicable for GX devices. Intel recommends not enabling it for GT devices. Enable RX/TX FIFO On/Off Enables the double width mode for the RX and TX FIFOs.
Page 57 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Range Description TX FIFO partially 2, 3, 4, 5 Specifies the partially empty threshold for the Enhanced PCS TX empty threshold FIFO. Enter the value at which you want the TX FIFO to flag a partially empty status.
Page 58 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Range Description Enable RX FIFO control On / Off When you turn on this option, Interlaken control word removal is word deletion enabled. When the Enhanced PCS RX FIFO is configured in...
Page 59 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Range Description Enable tx_enh_frame On / Off Enables the status output port. When the tx_enh_frame port Interlaken frame generator is enabled, this signal indicates the beginning of a new metaframe. This is an asynchronous signal.
Page 60 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 23. 10GBASE-R BER Checker Parameters Parameter Range Description Enable On / Off Enables the rx_enh_highber port. For 10GBASE-R transceiver rx_enh_highber port configuration rule, this signal is asserted to indicate a bit error...
Page 61 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 26. Interlaken Disparity Generator and Checker Parameters Parameter Range Description Enable Interlaken TX On / Off When you turn on this option, the Enhanced PCS enables the disparity generator disparity generator.
Page 62: Standard Pcs Parameters
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 29. KR-FEC Parameters Parameter Range Description Enable RX KR-FEC On/Off When you turn on this option, the decoder asserts both sync bits error marking (2'b11) when it detects an uncorrectable error. This feature increases the latency through the KR-FEC decoder.
Page 63 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 30. Standard PCS Parameters Note: For detailed descriptions of the optional ports that you can enable or disable, refer to the Standard PCS Ports on page 86 section. Parameter...
Page 64 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 32. Byte Serializer and Deserializer Parameters Parameter Range Description Enable TX byte Disabled Specifies the TX byte serializer mode for the Standard PCS. The serializer transceiver architecture allows the Standard PCS to operate at Serialize x2 double or quadruple the data width of the PMA serializer.
Page 65 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 35. Word Aligner and Bitslip Parameters Parameter Range Description Enable TX bitslip On / Off When you turn on this option, the PCS includes the bitslip function. The outgoing TX data can be slipped by the number of bits specified by the control signal.
Page 66 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 36. Bit Reversal and Polarity Inversion Parameter Range Description Enable TX bit reversal On / Off When you turn on this option, the 8B/10B Encoder reverses TX parallel data before transmitting it to the PMA for serialization.
Page 67: Pcs Direct
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Range Description threshold voltage that you specified. You can specify the signal detect threshold using a Quartus Prime Assignment Editor or by modifying the Quartus Settings File (.qsf) Table 37.
Page 68 PLLs. For example, you can change the reference clock input to the TX PLL. You can also change between the Standard and Enhanced datapaths. To enable Intel Arria 10 transceiver toolkit capability in the Native PHY IP core, you must enable the following options: •...
Page 69 Quartus. This option does not remove the requirement to specify Quartus Prime Setting File (.qsf) assignments for your analog settings. Refer to the Analog Parameter Settings chapter in the Arria 10 Transceiver PHY User Guide for details on using the QSF assignments. Table 42.
Page 70 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value Description Store Clicking this button saves or stores the current Native PHY parameter settings to the configuration profile specified by the Selected reconfiguration profile parameter. to selected profile...
Page 71 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value Description Pre-Emphasis First Post-Tap Fir_post_1t_neg Selects the polarity of the first post-tap for pre- Polarity emphasis Fir_post_1t_pos (31) Pre-Emphasis First Post-Tap 0-25 Selects the magnitude of the first post-tap for Magnitude pre-emphasis.
Page 72 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value Description Decision Feedback Equalizer Selects the co-efficient of the fixed tap 3 of the radp_dfe_fxtap3_0 (DFE) Fixed Tap 3 Co- Decision Feedback Equalizer (DFE) when radp_dfe_fxtap3_127 efficient operating in manual mode.
Page 73: Pma Ports
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.4.8. PMA Ports This section describes the PMA and calibration ports for the Arria 10 Transceiver Native PHY IP core. The following tables, the variables represent these parameters: • <n>—The number of lanes •...
Page 74 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Direction Clock Domain Description Input Asynchronous This port is available if you turn on Enable tx_pma_qpipullup[< tx_pma_qpipullup port (QPI) in the Transceiver Native PHY n>-1:0] IP core Parameter Editor. It is only used for Quick Path Interconnect (QPI) applications.
Page 75 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Direction Clock Domain Description Output Clock This port is available if you turn on Enable rx_ rx_pma_iqtxrx_clko pma_iqtxrx_clkout port in the Transceiver Native PHY IP core Parameter Editor. This output clock can be used to cascade the RX PMA output clock to the input of a PLL.
Page 76: Enhanced Pcs Ports
<d>—The serialization factor • <s>— The symbol size • <p>—The number of PLLs (34) Although the reset ports are not synchronous to any clock domain, Intel recommends that you synchronize the reset ports with the system clock. ® ® Intel Arria...
Page 77 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 49. Enhanced TX PCS: Parallel Data, Control, and Clocks Name Direction Clock Domain Description Input Synchronous to TX parallel data inputs from the FPGA fabric to the TX PCS. If...
Page 78 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Direction Clock Domain Description embedded in TX PCS. Both the synchronous header error and the CRC32 errors are inserted if the CRC-32 error insertion feature is enabled in the Transceiver Native PHY IP GUI.
Page 79 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Direction Clock Domain Description rx_coreclk rx_clkout Input Clock The FPGA fabric clock. Drives the read side of the RX FIFO. For rx_coreclkin Interlaken protocol, the frequency of this clock could be from datarate/67 to datarate/32.
Page 80 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Direction Clock Domain Description the FIFO This option is available when you select the following parameters: rx_coreclkin • Enhanced PCS Transceiver configuration rules rx_clkout specifies Interlaken • Enhanced PCS Transceiver configuration rules...
Page 81 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Direction Clock Domain Description the FIFO rx_coreclkin rx_clkout Input Synchronous to When asserted, the FIFO resets and begins searching rx_enh_fifo_align_cl the clock driving for a new alignment pattern. This signal is only valid r[<n>-1:0]...
Page 82 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 54. 10GBASE-R BER Checker Name Direction Clock Domain Description Output When asserted, indicates a bit error rate that is greater rx_enh_highber[<n>-1:0 rx_clkout than 10 . For the 10GBASE-R protocol, this BER rate occurs when there are at least 16 errors within 125 µs.
Page 83 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 • Transceiver PHY Reset Controller Interfaces on page 437 2.4.9.1. Enhanced PCS TX and RX Control Ports This section describes the bit encodings for different tx_control rx_control protocol configurations. When Enable simplified data interface is ON, all of the unused ports shown in the tables below, appear as a separate port.
Page 84 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 61. Bit Encodings for Basic Double Width Mode For basic double width mode, the total word length is 66-bit with 128-bit data and 4-bit synchronous header. Name Functionality Description...
Page 85 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Functionality Description Synchronization header error, metaframe error, A logic high (1'b1) indicates or CRC32 error status synchronization header error, metaframe error, or CRC32 error status. Block lock and frame lock status...
Page 86: Standard Pcs Ports
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Functionality Description [17:12] Unused [18] Synchronous header error status Active-high status signal that indicates a synchronous header error. [19] Block lock is achieved Active-high status signal indicating when Block Lock is achieved.
Page 87 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 In the following tables, the variables represent these parameters: • <n>—The number of lanes • <w>—The width of the interface • <d>—The serialization factor • <s>— The symbol size •...
Page 88 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 70. Standard PCS FIFO Name Direction Clock Domain Description Output Synchronous Indicates when the standard TX FIFO is full. tx_std_pcfifo_full[<n to the clock >-1:0] driving the write side of...
Page 89 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 72. 8B/10B Encoder and Decoder Name Direction Clock Domain Description Input tx_clkout is exposed if 8B/10B enabled and simplified data tx_datak tx_datak interface is set.When 1, indicates that the 8B/10B encoded word of tx_parallel_data is control.
Page 90 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Direction Clock Domain Description . For each 128-bit word, rx_parallel_data corresponds to rx_patterndetect rx_parallel_data[12] Output Asynchronous When asserted, indicates that the conditions required for rx_syncstatus[<n><w>/ synchronization are being met.
Page 91: Ip Core File Locations
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Direction Clock Domain Description receive circuitry receives all words in the reverse order. The bit reversal circuitry operates on the output of the word aligner. Input Asynchronous When asserted, the TX polarity bit is inverted. Only active tx_polinv[<n>-1:0]...
Page 92 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 26. Directory Structure for Generated Files <Project Directory> <your_ip_or_system_name>.qsys - Top-level IP variation file <your_ip_or_system_name>.sopcinfo <your_ip_name> - IP core variation files <your_ip_name>.cmp - VHDL component declaration file <your_ip_name>_bb - Verilog HDL black-box EDA synthesis file <your_ip_name>_inst - IP instantiation template file...
Page 93: Unused Transceiver Rx Channels
2.4.12. Unused Transceiver RX Channels To prevent performance degradation of unused transceiver RX channels over time, the following assignments must be added to an Arria 10 device QSF. You can either use a global assignment or per-pin assignments. set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON...
Page 94: Unsupported Features
The Interlaken interface is supported with 1 to 48 lanes running at data rates up to 12.5 Gbps per lane on Arria 10 devices. Interlaken is implemented using the Enhanced PCS. The Enhanced PCS has demonstrated interoperability with Interlaken ASSP vendors and third-party IP suppliers.
Page 95: Metaframe Format And Framing Layer Control Word
2.5.1. Metaframe Format and Framing Layer Control Word The Enhanced PCS supports programmable metaframe lengths from 5 to 8192 words. However, for stability and performance, Intel recommends you set the frame length to no less than 128 words. In simulation, use a smaller metaframe length to reduce simulation times.
Page 96 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 28. Framing Layer Metaframe Format Metaframe Length Control and Data Words The framing control words include: • Synchronization (SYNC)—for frame delineation and lane alignment (deskew) • Scrambler State (SCRM)—to synchronize the scrambler •...
Page 97: Interlaken Configuration Clocking And Bonding
32 31 2.5.2. Interlaken Configuration Clocking and Bonding The Arria 10 Interlaken PHY layer solution is scalable and has flexible data rates. You can implement a single lane link or bond up to 48 lanes together. You can choose a lane data rate up to 17.4 Gbps for GX devices and 25.8 Gbps for GT devices.
Page 98 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 32. 10X12.5 Gbps xN Bonding Native PHY Instance (10 Ch Bonded 12.5 Gbps) Transceiver PLL Instance (6.25 GHz) Transceiver Bank 1 Master ATX PLL TX Channel TX Channel TX Channel...
Page 99 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.5.2.2.1. TX FIFO Soft Bonding The MAC layer logic and TX soft bonding logic control the writing of the Interlaken word to the TX FIFO with (functions as a TX FIFO write enable)
Page 100 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 33. TX Soft Bonding Flow Exit from tx_digitalreset Deassert all lanes tx_enh_frame_burst_en Assert all lanes tx_enh_data_valid All lanes full? Deassert all lanes tx_enh_data_valid Any lane send new frame? tx_enh_frame...
Page 101 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 34. TX FIFO Pre-fill (6-lane Interface) Deassert tx_digitalreset tx_digitalreset tx_enh_data_valid tx_enh_fifo_full tx_enh_fifo_pfull tx_enh_fifo_empty tx_enh_fifo_pempty tx_enh_fifo_cnt 000000 1... 2... 3... 4... 5... 6... 7... 8... 9... a... b... c... d... e... ffffff...
Page 102 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 36. State Flow of the RX FIFO Deskew Exit from rx_digitalreset Deassert all Lane’s rx_enh_fifo_rd_en All Lane’s rx_enh_fifo_pempty Deasserted? Assert rx_enh_fifo_align_clr for at least 4 rx_coreclkin Cycles All Lane’s...
Page 103: How To Implement Interlaken In Arria 10 Transceivers
You should be familiar with the Interlaken protocol, Enhanced PCS and PMA architecture, PLL architecture, and the reset controller before implementing the Interlaken protocol PHY layer. Arria 10 devices provide three preset variations for Interlaken in the IP Parameter Editor: •...
Page 104 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 38. Signals and Ports of Native PHY IP for Interlaken Arria 10 Transceiver Native PHY reconfig_reset tx_cal_busy Hard Reconfiguration reconfig_clk rx_cal_busy Calibration Block Registers reconfig_avmm TX PMA TX Enhanced PCS...
Page 105 This figure shows the connection of all these blocks in the Interlaken PHY design example available on the Intel FPGA Wiki website. For the blue blocks, Intel provides an IP core. The gray blocks use the TX soft bonding logic that is included in the design example. The white blocks are your test logic or MAC layer logic.
Page 106: Design Example
Intel provides a PHY layer-only design example to help you integrate an Interlaken PHY into your complete design. The TX soft bonding logic is included in the design example. Intel recommends that you integrate this module into your design. The Interlaken Design Example is available on the Arria 10 Transceiver PHY Design Examples Wiki page.
Page 107: Native Phy Ip Parameter Settings For Interlaken
UG-01143 | 2018.06.15 2.5.5. Native PHY IP Parameter Settings for Interlaken This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values. Table 76.
Page 108 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value Enable tx_pma_qpipulldn port (QPI) Enable tx_pma_txdetectrx port (QPI) Enable tx_pma_rxfound port (QPI) Enable rx_seriallpbken port On / Off Table 78. RX PMA Parameters Parameter Value Number of CDR reference clocks...
Page 109 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value Enable tx_enh_fifo_pfull port On / Off Enable tx_enh_fifo_empty port On / Off Enable tx_enh_fifo_pempty port On / Off RX FIFO mode Interlaken RX FIFO partially full threshold from 10-29 (no less than pempty_threshold+8)
Page 110 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 82. Interlaken CRC-32 Generator and Checker Parameters Parameter Value Enable Interlaken TX CRC-32 generator Enable Interlaken TX CRC-32 generator error On / Off insertion Enable Interlaken RX CRC-32 checker...
Page 111: Ethernet
1 to 8 Selected reconfiguration profile 1 to 7 Related Information Using the Arria 10 Transceiver Native PHY IP Core on page 45 2.6. Ethernet The Ethernet standard comprises many different PHY standards with variations in signal transmission medium and data rates. The 1G/10GbE and 10GBASE-KR PHY IP Core enables Ethernet connectivity at 1 Gbps and 10 Gbps over backplanes.
Page 112: Gigabit Ethernet (Gbe) And Gbe With Ieee 1588V2
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 Gigabit Ethernet (GbE) is a high-speed local area network technology that provides data transfer rates of about 1 Gbps. GbE builds on top of the ethernet protocol, but increases speed tenfold over Fast Ethernet.
Page 113 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 43. Transceiver Channel Datapath and Clocking at 1250 Mbps for GbE, GbE with IEEE 1588v2 Transmitter PMA Transmitter Standard PCS FPGA Fabric PRBS Generator tx_coreclkin 625 MHz 125 MHz...
Page 114 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 The IEEE 802.3 specification requires GbE to transmit Idle ordered sets (/I/) continuously and repetitively whenever the gigabit media-independent interface (GMII) is Idle. This transmission ensures that the receiver maintains bit and word synchronization whenever there is no active data to be transmitted.
Page 115 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 45. Reset Condition n + 1 n + 3 n + 2 n + 4 clock tx_digitalreset tx_parallel_data K28.5 K28.5 K28.5 K28.5 Dx.y Dx.y K28.5 Dx.y K28.5 Dx.y K28.5 Dx.y...
Page 116 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 46. rx_syncstatus High Three Consecutive Ordered Sets Received to Achieve Synchronization rx_parallel_data rx_datak rx_syncstatus rx_patterndetect rx_disperr rx_errdetect Related Information Word Aligner on page 485 2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2 The 8B/10B decoder takes a 10-bit encoded value as input and produces an 8-bit data value and 1-bit control value as output.
Page 117 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.1.4. Rate Match FIFO for GbE The rate match FIFO compensates frequency Part-Per-Million (ppm) differences between the upstream transmitter and the local receiver reference clock up to 125 MHz ± 100 ppm difference.
Page 118 Rate Match FIFO on page 491 2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Arria 10 Transceivers You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing the GbE protocol.
Page 119 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Refer to Select and Instantiate the PHY IP Core on page 33. 2. Select GbE or GbE 1588 from the Transceiver configuration rules list located under Datapath Options, depending on which protocol you are implementing.
Page 120 2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2 This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Page 121 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 91. General and Datapath Options The first two sections of the Native PHY [IP] parameter editor for the Native PHY IP provide a list of general and datapath options to customize the transceiver.
Page 122 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value DFE adaptation mode disabled Number of fixed dfe taps Enable rx_pma_clkout port On/Off Enable rx_pma_div_clkout port On/Off rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66 Enable rx_pma_iqtxrx_clkout port...
Page 123 Enable RX polarity inversion On/Off Enable rx_polinv port On/Off Enable rx_std_signaldetect port On/Off All options under PCIe Ports Related Information Using the Arria 10 Transceiver Native PHY IP Core on page 45 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 124: 10Gbase-R, 10Gbase-R With Ieee 1588V2, And 10Gbase-R With Fec
10GBASE-R PHY functionality by using the presets of the Native PHY IP. The 10GBASE-R PHY IP is compatible with the 10-Gbps Ethernet MAC Intel FPGA IP Core Function. The complete PCS and PHY solutions can be used to interface with a third-party PHY MAC layer as well.
Page 125 10GBASE-R Register Mode • 10GBASE-R w/ KR-FEC Intel recommends that you use the presets for selecting the suitable 10GBASE-R variants directly if you are configuring through the Native PHY IP core. Figure 55. Transceiver Channel Datapath and Clocking for 10GBASE-R...
Page 126 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 The IEEE 1588 Precision Time Protocol (PTP) is supported by the preset of the Arria 10 transceiver Native PHY that configures 10GBASE-R PHY IP in IEEE-1588v2 mode. PTP is used for precise synchronization of clocks in applications such as: •...
Page 127 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Arria 10 10GBASE-R has the optional FEC variant that also targets the 10GBASE-KR PHY. This provides a coding gain to increase the link budget and BER performance on a broader set of backplane channels as defined in Clause 69. It provides additional margin to account for variations in manufacturing and environment conditions.
Page 128 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 58. Clock Generation and Distribution for 10GBASE-R with FEC Support Example using a 64-bit PCS-PMA interface width. 10GBASE-R Hard IP Transceiver Channel 64 Bit Data 8 Bit Control 10.3125 Gbps...
Page 129 RX PCS data driven by the RX recovered clock and RX XGMII data. Note: 10GBASE-R is the single-channel protocol that runs independently. Therefore Intel recommends that you use the presets for selecting the suitable 10GBASE-R variants directly. If it is being configured through the Native PHY IP, the channel bonding option should be disabled.
Page 130 You must design your own MAC and other layers in the FPGA to implement the 10GBASE-R, 10GBASE-R with 1588, or 10GBASE-R with KR FEC Transceiver Configuration Rule using the Native PHY IP. 1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog. Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
Page 131 6. Create a transceiver reset controller. You can use your own reset controller or use the Arria 10 Transceiver Native PHY Reset Controller IP. 7. Connect the Arria 10 Transceiver Native PHY to the PLL IP and the reset controller. Figure 61.
Page 132 2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values. Table 95.
Page 133 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 98. Enhanced PCS Parameters Parameter Range Enhanced PCS/PMA interface width 32, 40, 64 Note: 10GBASE-R with KR-FEC allows 64 only. FPGA fabric/Enhanced PCS interface width Enable Enhanced PCS low latency mode...
Page 134: Transceiver Configurations
Generation Options Parameters Parameter Range Generate parameter documentation file Related Information Using the Arria 10 Transceiver Native PHY IP Core on page 45 2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations Figure 63. High BER...
Page 135: 10Gbase-Kr Phy Ip Core
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 64. Block Lock Assertion This figure shows the assertion on signal when the Receiver detects the block delineation. rx_enh_blk_lock rx_parallel_data 0100009C0100009Ch 0707070707070707h rx_control tx_parallel_data 0707070707070707h tx_control rx_enh_highber rx_ready rx_enh_block_lock The following figures show Idle insertion and deletion.
Page 136 This topic provides performance and resource utilization for the IP. The following table shows the typical expected resource utilization for selected configurations using the Quartus Prime software v15.1 for Arria 10 devices. The numbers of ALMs and logic registers are rounded up to the nearest 100.
Page 137 500 ms of the specified time frame as required. Link Training (LT), IEEE 802.3 Clause 72 Arria 10 devices have soft link training IP that complies with the IEEE 802.3 Clause 72 standard training procedure. This IP includes: •...
Page 138 2.6.3.4. Parameterizing the 10GBASE-KR PHY This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values. The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the Backplane-KR or 1Gb/10Gb Ethernet variant.
Page 139 4. Click Generate HDL to generate the 10GBASE-KR PHY IP core top-level HDL file. Note: You might observe timing violations. If the timing path is within the IP, you can ignore these violations. This will be fixed in a future release of the Intel Quartus Prime software. Related Information •...
Page 140 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Name Options Description Enable rx_clkout port When you turn on this parameter, the port is rx_clkout enabled. Refer to the Clock and Reset Interfaces section for more information about this port.
Page 141 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Range Description Pause ability-C0 Depends upon MAC. Local device pause capability C2:0 = D12:10 of AN word. C0 is the same as PAUSE. Pause ability-C1 Depends upon MAC. Local device pause capability C2:0 = D12:10 of AN word.
Page 142 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Value Description PREPREVAL Specifies the preset Pre-tap value. The default value is 0. 0-15 INITMAINVAL Init VOD Specifies the initial V value. This value is set by the Initialize...
Page 143 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.3.5. 10GBASE-KR PHY Interfaces Figure 70. 10GBASE-KR Top-Level Signals 10GBASE-KR Top-Level Ports rx_serial_data xgmii_tx_dc[71:0] Transceiver tx_serial_data xgmii_tx_clk XGMII Serial Data xgmii_rx_dc[71:0] Interfaces xgmii_rx_clk mgmt_clk rx_block_lock mgmt_clk_reset rx_hi_ber mgmt_address[10:0] rx_is_lockedtodata Avalon-MM PHY...
Page 144 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Description Output Clock used to drive the 10G TX PCS and 1G TX PCS parallel data. For tx_pma_clkout example, when the hard PCS is reconfigured to the 10G mode without FEC enabled, the frequency is 257.81 MHz.
Page 145 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Clock Domain Description recommends that you connect it to a PLL for use with the Triple Speed Ethernet IP function. The frequency is 125 MHz for 1G and 156.25 MHz for 10G. This clock is driven from the MAC.
Page 146 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 117. RX XGMII Mapping to Standard SDR XGMII Interface The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface. This table shows the mapping of this non-standard format to the standard SDR XGMII interface.
Page 147 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Clock Domain Description Output Synchronous to When asserted, this signal indicates the following led_panel_link behavior: mgmt_clk Mode Behavior 1000 Base-X without Auto- When asserted, indicates negotiation successful link synchronization.
Page 148 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Clock Domain Description Output Synchronous to When you enable 1588, this signal outputs the real time tx_latency_adj_10 latency in XGMII clock cycles (156.25 MHz) for the TX...
Page 149 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Clock Domain Description Input Synchronous to Input data. mgmt_writeda mgmt_clk ta[31:0] Output Synchronous to Output data. mgmt_readdat mgmt_clk a[31:0] Input Synchronous to Write signal. Active high. mgmt_write...
Page 150 0100: 10GBASE-R • 0101: 10GBASE-KR • 1100: 10GBASE-KR FEC When set to 1, it enables the Arria 10 HSSI reconfiguration Enable Arria 10 calibration as part of the PCS dynamic reconfiguration. 0 skips Calibration the calibration when the PCS is reconfigured.
Page 151 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr 31:12 — Reserved — 0x4B5 to Reserved for 40G KR Intentionally left empty for address compatibility with 40G 0x4BF MAC + PHY KR solutions. 0x4C0 When set to 1, enables Auto Negotiation function. The default AN enable value is 1.
Page 152 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr When set to 1, the transceiver PHY is able to perform Auto AN Ability Negotiation. When set to 0, the transceiver PHY i s not able to perform Auto Negotiation.
Page 153 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr 30:28 AN_PAUSE value with which to override the current value. The Override following bits are defined: AN_PAUSE[2:0] • Bit-28 = = Pause Ability AN_PAUSE [0] •...
Page 154 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr 0x4CA 31:0 The AN RX state machine receives these bits from the link LP Next page high partner. Bits [31:0] correspond to page bits [47:16] 0x4CB...
Page 155 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr • 101 = 32 • 110 = 64 • 111 = 128 The default value is 101. When set to 1, PMA values (VOD, Pre-tap, Post-tap) are not...
Page 156 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr 28:24 Defines the CTLE value used by the link training algorithm Manual CTLE when in manual CTLE mode. These bits are only effective when 0x4D0[22] is set to 1.
Page 157 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr 0x4D3 Specifies the number of training frames to examine for bit ber_time_frames errors on the link for each step of the equalization settings. Used only when ber_time_k_frames is 0.The following values are defined: •...
Page 158 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr • [5:4]: Coefficient (post-tap) — 2'b11: Maximum — 2'b01: Minimum — 2'b10: Updated — 2'b00: Not updated • [3:2]: Coefficient (0) (same encoding as [5:4]) •...
Page 159 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr • [5:4]: Coefficient (+1) — 2'b11: Maximum — 2'b01: Minimum — 2'b10: Updated — 2'b00: Not updated • [3:2]: Coefficient (0) (same encoding as [5:4]) •...
Page 160 All registers in the physical coding sub-layer (PCS) and physical x3FF registers media attachment (PMA) that you can dynamically reconfigure are in this address space. Refer to the Arria 10 Dynamic Transceiver Reconfiguration chapter for further information. Related Information Reconfiguration Interface and Dynamic Reconfiguration on page 502 2.6.3.6.3.
Page 161 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Addr Access Name Description 0x482 High BER status. When set to 1, the PCS reports a high HI_BER BER. When set to 0, the PCS does not report a high BER.
Page 162 156.25 MHz XGMII clock from the 10G reference clock. Unlike in the 10GBASE-KR PHY IP core for Stratix V devices, no Memory Initialization Files (.mif) are required for the 10GBASE-KR design in Arria 10 devices. 6. Complete the design by creating a top level module to connect all the IP (10GBASE-KR PHY IP core, PLL IP core, and Reset Controller) blocks.
Page 163 For more information about latency in the MAC as part of the Precision Time Protocol implementation. 2.6.3.9. Simulation Support The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Intel-supported simulators for this Quartus Prime software release: • ModelSim Verilog •...
Page 164: 1-Gigabit/10-Gigabit Ethernet (Gbe) Phy Ip Core
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 • VCS VHDL • NCSIM Verilog • NCSIM VHDL simulation When you generate a 1G/10GbE or 10GBASE-KR PHY IP core, the Quartus Prime software optionally generates an IP functional simulation model.
Page 165 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 72. Top Level Modules of the 1G/10GbE PHY IP Function The Enhanced PCS receives and transmits XGMII data. The Standard PCS receives and transmits GMII data. Intel Device with 10.3125-Gbps Transceivers...
Page 166 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.4.2. 1G/10GbE PHY Performance and Resource Utilization This topic provides performance and resource utilization for the 1G/10GbE PHY IP core in Arria 10 devices. The following table shows the typical expected resource utilization for selected configurations using the Quartus Prime software version 15.1.
Page 167 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Sequencer The Sequencer controls the start-up sequence of the PHY IP, including reset and power-on. It selects which PCS (1G or 10G) and PMA interface is active. The Sequencer interfaces to the reconfiguration block to request a change from one data rate to the other data rate.
Page 168 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Related Information • Arria 10 Enhanced PCS Architecture on page 461 • Arria 10 Standard PCS Architecture on page 479 • Arria 10 PMA Architecture on page 447 • 10-Gbps Ethernet MAC IP Function User Guide.
Page 169 Native tx_div_clkout tx_coreclkin PHY. Input The clock for the XGMII RX interface with the MAC. Intel xgmii_rx_clk recommends connecting it directly to a PLL for use with TSE. This drives of the native PHY. Its frequency is 156.25 or rx_coreclkin 312.5 MHz.
Page 170 2.6.4.5. Parameterizing the 1G/10GbE PHY This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values. The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the Backplane-KR or 1Gb/10Gb Ethernet variant.
Page 171 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Note: You might observe timing violations. If the timing path is within the IP, you can ignore these violations. This will be fixed in a future release of the Intel Quartus Prime software. Related Information •...
Page 172 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Name Options Description Reference clock frequency 644.53125 MHz Specifies the input reference clock frequency. The default is 322.265625 MHz. 322.265625 MHz Enable additional control When you turn this option on, the core includes the and status ports output.
Page 173 Enable PCS-Mode port Enables or disables the PCS-Mode port. 2.6.4.5.5. PHY Analog Parameters You can specify analog parameters using the Intel Quartus Prime Assignment Editor, the Pin Planner, or the Intel Quartus Prime Settings File (.qsf). ® ® Intel...
Page 174 _hw.tcl file. If you turn on Show signals, the block diagram displays all top-level signal names. For more information about _hw.tcl files, refer to the Component Interface Tcl Reference chapter in volume 1 of the Intel Quartus Prime Handbook.
Page 175 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.4.6.1. Clock and Reset Interfaces Table 135. Clock and Reset Signals Signal Name Direction Description Input High speed clock from the 10G PLL to drive 10G PHY TX PMA. The tx_serial_clk_10g frequency of this clock is 5.15625 GHz.
Page 176 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.4.6.2. Data Interfaces Table 136. XGMII Signals The MAC drives the TX XGMII signals to the 10GbE PHY. The 10GbE PHY drives the RX XGMII signals to the MAC. Signal Name...
Page 177 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name SDR XGMII Signal Name Description Lane 6 data xgmii_tx_dc[61:54] xgmii_sdr_data[55:48] Lane 6 control xgmii_tx_dc[62] xgmii_sdr_ctrl[6] Lane 7 data xgmii_tx_dc[70:63] xgmii_sdr_data[63:56] Lane 7 control xgmii_tx_dc[71] xgmii_sdr_ctrl[7] Table 138. RX XGMII Mapping to Standard SDR XGMII Interface The 72-bit RX XGMII data bus format is different from the standard SDR XGMII interface.
Page 178 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Description Output The GMII RX error signal. Synchronous to gmii_rx_err tx_clkout Output 10-bit character error. Asserted for one led_char_err rx_clkout_1g cycle when an erroneous 10-bit character is detected.
Page 179 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Clock Domain Description Mode Behavior SGMII mode without Auto- When asserted, indicates negotiation successful link synchronization. 1000 Base-X with Auto- Clause 37 Auto-negotiation negotiation status. The PCS function asserts this signal when auto-negotiation completes.
Page 180 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Clock Domain Description Output Synchronous to When you enable 1588, this signal outputs the real time tx_latency_adj_10 latency in XGMII clock cycles (156.25 MHz) for the TX...
Page 181 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Clock Domain Description • Turn on Enable internal PCS reconfiguration logic Input Synchronous to When asserted, initiates reconfiguration of the PCS. start_pcs_reconf Sampled with the . This signal is only exposed...
Page 182 0100: 10GBASE-R • 0101: 10GBASE-KR • 1100: 10GBASE-KR FEC When set to 1, it enables the Arria 10 HSSI reconfiguration Enable Arria 10 calibration as part of the PCS dynamic reconfiguration. 0 skips the Calibration calibration when the PCS is reconfigured.
Page 183 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr When set to 1, indicates that the 10GBASE-KR PHY supports FEC. KR FEC ability Set as parameter . For more information, refer to SYNTH_FEC 170.0 Clause 45.2.1.84 of IEEE 802.3ap-2007.
Page 184 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr When asserted, AN has completed. When 0, AN is in progress. For AN Complete more information, refer to bit 7.1.5 in Clause 73.8 of IEEE 802.3ap-2007.
Page 185 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr 30:28 AN_PAUSE value to override. The following bits are defined: Override • Bit-28 = = Pause Ability AN_PAUSE[2:0] AN_PAUSE [0] • Bit-29 = = Asymmetric Direction AN_PAUSE [1] •...
Page 186 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr • A0 1000BASE-KX • A1 10GBASE-KX4 • A2 10GBASE-KR • A3 40GBASE-KR4 • A4 40GBASE-CR4 • A5 100GBASE-CR10 • A24:6 are reserved For more information, refer to Clause 73.6.4 and AN LP base page ability registers (7.19-7.21) of Clause 45 of IEEE 802.3ap-2007.
Page 187 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr The default value is 010. When set to 1, PMA values (VOD, pre-tap, post-tap) are not disable Initialize initialized upon entry into the state. This Training_Failure...
Page 188 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr When set to 1, a training failure has been detected. When set to Link Training 0, a training failure has not been detected. For more information,...
Page 189 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr For more information, refer to bit 10G BASE-KR LD coefficient update register bits (1.154.5:0) in Clause 45.2.1.80.3 of IEEE 802.3ap-2007. RO or When set to 1, requests the link partner coefficients be set to LD Initialize configure the TX equalizer to its INITIALIZE state.
Page 190 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Name Description Addr 0x4D4 RO or When set to 1, the local device TX coefficients are set to a state LP Preset where equalization is turned off. Preset coefficients are used.
Page 191 All registers in the physical coding sub-layer (PCS) and physical x3FF registers media attachment (PMA) that you can dynamically reconfigure are in this address space. Refer to the Arria 10 Dynamic Transceiver Reconfiguration chapter for further information. Related Information Reconfiguration Interface and Dynamic Reconfiguration on page 502 ®...
Page 192 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.4.7.3. Enhanced PCS Registers Table 147. Enhanced PCS Registers Addr Access Name Description 0x480 31:0 Because the PHY implements a single channel, this Indirect_addr register must remain at the default value of 0 to specify logical channel 0.
Page 193 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Addr Name Description Pause support for the local device. The following PS2,PS1 encodings are defined for PS1/PS2: • PS1=0 / PS2=0: Pause is not supported • PS1=0 / PS2=1: Asymmetric pause toward link partner •...
Page 194 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Addr Name Description Link partner capability: COPPER_DUPLEX_STATUS • 1: copper interface is capable of full-duplex operation • 0: copper interface is capable of half-duplex operation Note: The PHY IP Core does not support half duplex operation because it is not supported in SGMII mode of the 1G/10G PHY IP core.
Page 195 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 148. 1G Data Mode Addr Name Description 0x4A8 When set, the TX interface inverts the polarity of tx_invpolarity the TX data to the 8B/10B encoder. When set, the RX channels inverts the polarity of rx_invpolarity the received data to the 8B/10B decoder.
Page 196 Avalon-MM interface that you can use to read and write to PHY registers. All read and write operations must adhere to the Avalon specification. 2. Instantiate a reset controller using the Transceiver Reset Controller Intel FPGA IP Core in the IP Catalog. Connect the power and reset signals between the 1G/ 10GbE PHY and the reset controller.
Page 197 Arria 10 Avalon-MM Interface for PCIe* Solutions 2.6.4.11. Design Example Intel provides a design example to assist you in integrating your Ethernet PHY IP into your complete design. The MAC and PHY design example instantiates the 1G/10GbE PHY IP along with the 1G/10G Ethernet MAC and supporting logic.
Page 198 Divide CH3: PHY_ADDR = 0x3 Related Information Arria 10 Transceiver PHY Design Examples 2.6.4.12. Simulation Support The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Intel-supported simulators for this Quartus Prime software release: • ModelSim Verilog • ModelSim VHDL •...
Page 199: 2.5G/5G/10G Multi-Rate Ethernet Phy Ip Core
Soft Logic 125-MHz 322-MHz Reference Clock Reference Clock Related Information • Using the Arria 10 Transceiver Native PHY IP Core on page 45 • Recommended Reset Sequence on page 418 • Low Latency Ethernet 10G MAC User Guide Describes the Low Latency Ethernet 10G MAC IP Core.
Page 200: Release Information
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Feature Description 32-bit XGMII for 1G/2.5G/5G/10G (USXGMII). 64-bit XGMII for 10G. Network-side interface 1.25 Gbps for 1G. 3.125 Gbps for 2.5G. 10.3125 Gbps for 1G/2.5G/5G/10G (USXGMII). ® Avalon Memory-Mapped (Avalon-MM) Provides access to the configuration registers of the PHY.
Page 201 (USXGMII) 2.6.5.2. Using the IP Core The Intel FPGA IP Library is installed as part of the Intel Quartus Prime installation process. You can select the 1G/2.5G/5G/10G Multi-rate Ethernet IP core from the library and parameterize it using the IP parameter editor.
Page 202 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Name Value Description Connect to NBASE-T PHY On, Off Select this option when the external PHY is NBASE-T compatible. This parameter is enabled for 1G/2.5G/5G/10G (USXGMII) modes. PHY ID (32 bit)
Page 203: Configuration Registers
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 For the 1G/2.5G/5G/10G operating mode, constrain the PHY for the 10G datapath as well as the 1G/2.5G datapath. Refer to the example provided: <Installation Directory> /ip/altera/ethernet/alt_mge_phy/example/ alt_mge_phy_multi_speed_10g.sdc 2.6.5.2.3. Changing the PHY's Speed You can change the PHY's speed through the reconfiguration block.
Page 204 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Addr Name Description Access HW Reset Value • Bit [9]: . Set this bit RESTART_AUTO_NEGOTIATION to 1 to restart auto-negotiation. The PHY clears the bit as soon as auto-negotiation is restarted.
Page 205 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Addr Name Description Access HW Reset Value • Bits [8:7]: . The PAUSE support. — 00: No PAUSE. — 01: Symmetric PAUSE. — 10: Asymmetric PAUSE towards the link partner.
Page 206 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Addr Name Description Access HW Reset Value Bit [4:2]: is the operating speed of USXGMII_SPEED the PHY in USXGMII mode and is set USE_USXGMII_AN to 0. • 3’b000: Reserved •...
Page 207 2.6.5.3.1. Register Map (37) You can access the 16-bit/32-bit configuration registers via the Avalon-MM interface. (37) These registers are identical to the Intel Arria 10 variation of 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP core. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 208 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 156. Register Map Address Range Usage Configuration 2.5G, 1G/2.5G, 10M/ 100M/1G/2.5, 10M/ 0x00 : 0x1F 1000BASE-X/SGMII 100M/1G/2.5G/10G (MGBASE-T), 1G/2.5G/10G (MGBASE-T) 0x400 : 0x41F USXGMII 1G/2.5G/5G/10G (USXGMII) 0x461 Serial Loopback 1G/2.5G/5G/10G (USXGMII)
Page 209 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.5.4.1. Clock and Reset Signals Table 158. Clock and Reset Signals Signal Name Direction Width Description Clock signals Output GMII TX clock, derived from tx_clkout . Provides 156.25 MHz tx_serial_clk[1:0] timing reference for 2.5GbE;...
Page 210 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Width Description Input Connect this signal to the Transceiver PHY Reset tx_digitalreset Controller IP core. When asserted, triggers an asynchronous reset to the digital logic on the TX path.
Page 211 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Width Description Output The latency of the PHY excluding the PMA block on gmii16b_tx_latency the TX datapath: • Bits [21:10]: The number of clock cycles. • Bits [9:0]: The fractional number of clock cycles.
Page 212 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Width Description • 8 bits for 1G/2.5G/10G configurations. • 4 bits for 1G/2.5G/5G/10G configurations. Output Indicates valid data on xgmii_tx_valid xgmii_tx_control from the MAC. xgmii_tx_data Your logic/MAC must toggle the valid data as...
Page 213 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.5.4.5. Status Signals Table 162. Status Signals Signal Name Direction Clock Width Description Domain Output Asserted when a 10-bit character error is led_char_err detected in the RX data. Output Synchronous...
Page 214: Xaui Phy Ip Core
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.5.4.8. Avalon-MM Interface Signals The Avalon-MM interface is an Avalon-MM slave port. This interface uses word addressing and provides access to the 16-bit configuration registers of the PHY. Table 165.
Page 215 Medium Dependent Interface Medium 10 Gbps Intel's XAUI PHY IP core implements the IEEE 802.3 Clause 48 specification to extend the operational distance of the XGMII interface and reduce the number of interface signals. XAUI extends the physical separation possible between the 10 Gbps Ethernet MAC function and the Ethernet standard PHY component to one meter.
Page 216 1-bit control code at both the positive and negative edge (double data rate) of the 156.25 MHz interface clock. Arria 10 transceivers and a soft PCS solution in a XAUI configuration do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008 specification.
Page 217 UG-01143 | 2018.06.15 Figure 84. Implementation of the XGMII Specification in Arria 10 Devices Configuration The ATX PLL is only supported to drive the internal transceiver. The FPLL is only supported to drive . Both the ATX PLL and the FPLL must be clocked by the same reference...
Page 218 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Transmitter and Receiver State Machines In a XAUI configuration, the Arria 10 soft PCS implements the transmitter and receiver state diagrams shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008 specification.
Page 219: Xaui Phy Release Information
00D7 Vendor ID 6AF7 2.6.6.4. XAUI PHY Device Family Support IP cores provide either final or preliminary support for target Intel device families. These terms have the following definitions: • Final support—Verified with final timing models for this device. •...
Page 220 (From the ×1 Clock Lines) Parallel and Serial Clocks Note: 1. Use the ATX PLL as the transmit PLL for XAUI support in Arria 10 devices. Note: When configuring ATX PLL, the PMA width setting must be set to 20-bit per transceiver channel.
Page 221: Parameterizing The Xaui Phy
2.6.6.7. Parameterizing the XAUI PHY This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values. Complete the following steps to configure the XAUI PHY IP core in the IP Catalog: 1.
Page 222: Xaui Phy General Parameters
Analog Parameters Advanced Options Parameters 5. Click Finish to generate your customized XAUI PHY IP core. Related Information • Using the Arria 10 Transceiver Native PHY IP Core on page 45 • XAUI PHY General Parameters on page 222 •...
Page 223 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 87. XAUI Top-Level Signals—Soft PCS and PMA XAUI Top-Level Signals xgmii_tx_dc[71:0] SDR TX XGMII xaui_rx_serial_data[3:0] Transceiver xgmii_tx_clk xaui_tx_serial_data[3:0] Serial Data xgmii_rx_dc[71:0] SDR RX XGMII rx_channelaligned xgmii_rx_clk RX Status rx_disperr[7:0]...
Page 224: Sdr Xgmii Tx Interface
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.6.9.1. SDR XGMII TX Interface Table 171. SDR TX XGMII Interface Signal Name Direction Description Input Contains 4 lanes of data and control for XGMII. Each lane consists of xgmii_tx_dc[71:0] 16 bits of data and 2 bits of control.
Page 225: Xaui Phy Pma Channel Controller Interface
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.6.6.9.4. XAUI PHY Clocks, Reset, and Powerdown Interfaces Figure 89. Clock Inputs and Outputs for IP Core with Soft PCS phy_mgmt_clk XAUI Soft IP Core pll_ref_clk pll_ref_clk Soft PCS xgmii_tx_clk...
Page 226: Xaui Phy Register Interface And Register Descriptions
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Signal Name Direction Description signal is 2 bits wide per channel for a rx_disperr total of 8 bits per XAUI link. Synchronous to mgmt_clk Output When asserted, indicates an 8B/10B code group rx_errdetect[7:0] violation.
Page 227 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 178. XAUI PHY IP Core Registers Word Bits Register Name Description Addr Reset Control Registers–Automatic Reset Controller 0x041 [31:0] Bit mask for reset registers at addresses 0x042 and reset_ch_bitmask 0x044.
Page 228: Acronyms
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Word Bits Register Name Description Addr [7:0] Records the synchronization status of the syncstatus[7:0] corresponding bit. The RX sync status register has 1 bit per channel for a total of 4 bits per soft XAUI link;...
Page 229: Pci Express (Pipe)
Link partner, to which the LD is connected. Media Access Control. Media independent interface. Open System Interconnection. Physical Coding Sublayer. Physical Layer in OSI 7-layer architecture, also in Intel device scope is: PCS + PMA. Physical Medium Attachment. Physical Medium Dependent. SGMII Serial Gigabit Media Independent Interface.
Page 230: Transceiver Channel Datapath For Pipe
• Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express • Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface 2.7.1. Transceiver Channel Datapath for PIPE Figure 90. Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations...
Page 231: Supported Pipe Features
Power state management Receiver PIPE status encoding pipe_rxstatus[2:0] Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate continued... (38) You must enable scrambling/descrambling in Gen1/Gen2 when using Arria 10 PCIe Gen3 configurations. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 232 2'b00 on the input signal initiates a data rate switch from Gen2 to Gen1. 2.7.2.1.2. Transmitter Electrical Idle Generation The PIPE interface block in Arria 10 devices puts the transmitter buffer in an electrical idle state when the electrical idle input signal is asserted. During electrical idle, the transmitter buffer differential and common mode output voltage levels are compliant with the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data rates.
Page 233 PIPE configuration. The PCIe specification requires the physical layer device to implement power-saving measures when the P0 power state transitions to the low power states. Arria 10 transceivers do not implement these power-saving measures except for putting the transmitter buffer in electrical idle mode in the lower power states.
Page 234 PIPE 2.0 specifications. 2.7.2.1.7. Gen1 and Gen2 Clock Compensation In compliance with the PIPE specification, Arria 10 receiver channels have a rate match FIFO to compensate for small clock frequency differences up to ±300 ppm between the upstream transmitter and the local receiver clocks.
Page 235 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 93. Rate Match Insertion The figure below shows an example of rate match insertion in the case where two SKP symbols must be inserted. Only one /K28.0/ SKP symbol is inserted per SKP ordered set received.
Page 236 Intel PHY Interface for the PCI Express* (PIPE) Architecture PCI Express 2.0 2.7.2.2. Gen3 Features The following subsections describes the Arria 10 transceiver block support for PIPE Gen3 features. The PCS supports the PIPE 3.0 base specification. The 32-bit wide PIPE 3.0-based interface controls PHY functions such as transmission of electrical idle, receiver detection, and speed negotiation and control.
Page 237 This section provides an overview of auto rate change between PIPE Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps) modes. In Arria 10 devices, there is one ASN block common to the Standard PCS and Gen3 PCS, located in the PMA PCS interface that handles all PIPE speed changes. The PIPE interface clock rate is adjusted to match the data throughput when a rate switch is requested.
Page 238 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 The sequence of speed change between Gen1, Gen2, and Gen3 occurs as follows: 1. The PHY-MAC layer implemented in FPGA fabric requests a rate change through pipe_rate[1:0] 2. The ASN block waits for the TX FIFO to flush out data. Then the ASN block asserts the PCS reset.
Page 239 2.7.2.2.7. Gearbox As per the PIPE 3.0 specification, for every 128 bits that are moved across the Gen3 PCS, the PHY must transmit 130 bits of data. Intel uses the pipe_tx_data_valid signal every 16 blocks of data to transmit the built-up backlog of 32 bits of data.
Page 240: How To Connect Tx Plls For Pipe Gen1, Gen2, And Gen3 Modes
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.7.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes Figure 101. Use ATX PLL or fPLL for Gen1/Gen2 x1 Mode X1 Network Ch 5 fPLL1 ATX PLL1...
Page 241 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 102. Use ATX PLL or fPLL for Gen1/Gen2 x4 Mode Network Network Ch 5 Ch 4 Connections Done via X1 Network fPLL1 Master Ch 3 ATX PLL1 Ch 2...
Page 242 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 103. Use ATX PLL or fPLL for Gen1/Gen2 x8 Mode Ch 5 Ch 4 Master Ch 3 Transceiver bank Ch 2 Connections Done via X1 Network fPLL1 Master Use Any...
Page 243 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 104. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x1 Mode X1 Network Ch 5 fPLL1 ATX PLL1 Ch 4 Master CGB1 Ch 3 Ch 2 fPLL0 Master Ch 1...
Page 244 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 105. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x4 Mode Network Network Ch 5 Ch 4 Connections Done via X1 Network fPLL1 Master Ch 3 ATX PLL1 Ch 2...
Page 245 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 106. Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x8 Mode Ch 5 Ch 4 Master Ch 3 Transceiver bank Ch 2 Connections Done via X1 Network fPLL1 Master Ch 1...
Page 246: How To Implement Pci Express (Pipe) In Arria 10 Transceivers
You must be familiar with the Standard PCS architecture, Gen3 PCS architecture, PLL architecture, and the reset controller before implementing the PCI Express protocol. 1. Go to the IP Catalog and select the Arria 10 Transceiver Native PHY IP Core. Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
Page 247 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 107. Connection Guidelines for a PIPE Gen3 Design pll_refclk ATX PLL fPLL Arria 10 and Master (Gen1/Gen2) Transceiver CGB (Gen3) Native PHY tx_bonding_clocks tx_bonding_clocks pipe_hclk_in pll_pcie_clk mcgb_aux_clk tx_serial_clk Reset Controller (2) Notes: (1).
Page 248: Native Phy Ip Parameter Settings For Pipe
Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Page 249 Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Page 250 Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Page 251 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE FPGA Fabric / Standard TX PCS interface 8, 16 width FPGA Fabric / Standard RX PCS interface 8, 16 width Enable Standard PCS low latency mode...
Page 252 Simplified Interface is enabled. tx_parallel_data Related Information • How to Place Channels for PIPE Configurations on page 268 • Using the Arria 10 Transceiver Native PHY IP Core on page 45 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 253: Fpll Ip Parameter Core Settings For Pipe
Parameter Settings for Arria 10 fPLL IP core in PIPE Gen1, Gen2, Gen3 modes This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Page 254 Generate C Header file Generate MIF (Memory Initialize file) Generation Options Generate parameter Enable Enable Enable documentation file Related Information Using the Arria 10 Transceiver Native PHY IP Core on page 45 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 255: Atx Pll Ip Parameter Core Settings For Pipe
Parameters for Arria 10 ATX PLL IP core in PIPE Gen1, Gen2, Gen3 modes This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values.
Page 256 Generate C Header file Generate MIF (Memory Initialize file) Generation Options Generate parameter documentation file Enable Enable Enable Related Information Using the Arria 10 Transceiver Native PHY IP Core on page 45 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 257: Native Phy Ip Ports For Pipe
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.7.8. Native PHY IP Ports for PIPE Figure 108. Signals and Ports of Native PHY IP for PIPE Arria 10 Transceiver Native PHY reconfig_reset Reconfiguration Nios II Hard tx_cal_busy reconfig_clk...
Page 258 Table 190. Ports for Arria 10 Transceiver Native PHY in PIPE Mode This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter settings. Port...
Page 259 After power-up, asserting this signal starts a loopback operation. Refer to pipe_tx_detectrx_loopba tx_coreclkin section 6.4 of the Intel PHY Interface for PCI ck [(N-1):0] Express (PIPE) for a timing diagram. Active High Asserted for one cycle to set the running disparity to negative.
Page 260 In Gen3 capable designs, the TX de-emphasis for Gen2 data rate is always -6 dB. The TX de-emphasis for Gen1 data rate is always -3.5 dB. Refer to section 6.6 of Intel PHY Interface for PCI Express (PIPE) Architecture for more information. continued...
Page 261 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Port Direction Clock Domain Description Note: Intel recommends transmitting Preset P8 coefficients for Arria 10 receiver to recover data successfully. This is used to trigger CTLE adaptation in Phase2 (EP) /Phase 3 (RP) to achieve...
Page 262 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Port Direction Clock Domain Description The data and control indicator. For Gen1 or Gen2, when 0, indicates that is data, when 1, rx_parallel_data indicates that rx_parallel_data control. , or rx_datak[3:0]...
Page 263 Disabled for more details. Table 191. Bit Mappings When the Simplified Interface Is Disabled This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values. Signal Name...
Page 264: Fpll Ports For Pipe
2.7.9. fPLL Ports for PIPE Table 192. fPLL Ports for PIPE This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter settings. Port Direction Clock Domain...
Page 265 For Gen3x2, x4, x8 connect the output pcie_sw_done from ATX PLL to the input of Native PHY. pipe_sw_done Related Information Using the Arria 10 Transceiver Native PHY IP Core on page 45 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 266: Atx Pll Ports For Pipe
2.7.10. ATX PLL Ports for PIPE Table 193. ATX PLL Ports for PIPE This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter settings. Port...
Page 267: Preset Mappings To Tx De-Emphasis
ATX PLL to pcie_sw_done input of Native PHY. pipe_sw_done Related Information Using the Arria 10 Transceiver Native PHY IP Core on page 45 2.7.11. Preset Mappings to TX De-emphasis Table 194. Arria 10 Preset Mappings to TX De-emphasis...
Page 268: How To Place Channels For Pipe Configurations
— When VCCR_GXB and VCCT_GXB are set to 0.95 V, the non-PCIe channels in those banks cannot be used. For channel placement guidelines when using Arria 10 Hard IP for PCIe, refer to the PCIe User Guide. For ATX PLL placement restrictions, refer to the section "Transmit PLL Recommendations Based on Data Rates"...
Page 269 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 195. Logical PCS Master Channel for PIPE Configuration PIPE Configuration Logical PCS Master Channel # (default) (44) (44) (44) (44) The following figures show the default configurations: Figure 109. x2 Configuration...
Page 270 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 110. x4 Configuration The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master Channel number 2 must be specified as Physical channel 4.
Page 271 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 111. x8 Configuration For x8 configurations, Intel recommends you choose a master channel that is a maximum of four channels away from the farthest slave channel. fPLL Master Transceiver bank...
Page 272 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 112. x4 Alternate Configuration The figure below shows an alternate way of placing 4 bonded channels. In this case, the logical PCS Master Channel number 2 must be specified as Physical channel 1.
Page 273 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 113. x4 Configuration with the Master Channel Adjacent to a Hard IP The figure below shows the placement of a x4 PIPE configuration with the Logical PCS Master Channel that is adjacent to a Hard IP.
Page 274: Phy Ip Core For Pcie (Pipe) Link Equalization For Gen3 Data Rate
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 114. x4 Configuration with the Master Channel not Adjacent to a Hard IP The figure below shows the placement of a x4 PIPE configuration with the Logical PCS Master Channel that is not adjacent to a Hard IP.
Page 275 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Phase 0 Phase 0 includes the following steps: 1. The upstream component enters Phase 0 of equalization during Recovery.Rcvrconfig by sending EQ TS2 training sets with starting presets for the downstream component.
Page 276 Training Sets. The default Full Swing (FS) value advertised by the Intel device is 60 and Low Frequency (LF) is 20. The three rules for transmitter coefficients are: a.
Page 277: Using Transceiver Toolkit (Ttk)/System Console/Reconfiguration Interface To Manually Tune Arria 10 Pcie Designs (Hard Ip(Hip) And Pipe) (For Debug Only)
Gen2 (directed or not) Note: Intel recommends that you use CTLE in adaptive mode for Gen3 speed. If you want to use CTLE in manual mode for Gen3 speed, then you must set = 3’b000 and set the CTLE 4S AC gain value pipe_g3_rxpresethint[2:0] •...
Page 278 - 0 positive Note: You must set the attribute located at register address user_fir_coeff_ctrl_sel 0x105[7] back to 1’b1 to allow the Arria 10 PCI Express PIPE design to listen to the port on each channel for normal PCIe operation. pipe_g3_txdeemph[17:0] Table 199.
Page 279: Cpri
Note: You must set the attribute located at register address 0x161[2] back rrx_pcie_eqz to 1’b1 to allow the Arria 10 PCIe PIPE design to listen to the port on each channel for normal PCIe operation. pipe_g3_rxpresethint[2:0] Related Information •...
Page 280: Transceiver Channel Datapath And Clocking For Cpri
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.8.1. Transceiver Channel Datapath and Clocking for CPRI Figure 115. Transceiver Channel Datapath and Clocking for CPRI Transmitter PMA Transmitter Standard PCS FPGA Fabric PRBS tx_coreclkin Generator 245 MHz tx_clkout...
Page 281: Supported Features For Cpri
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.8.1.1. TX PLL Selection for CPRI Choose a transmitter PLL that fits your required data rate. Table 202. TX PLL Supported Data Rates ATX and fPLL support the clock bonding feature.
Page 282 Lower delay uncertainty is always desired for increased spectrum efficiency and bandwidth. The Arria 10 devices are designed with features to minimize the delay uncertainty for both RECs and REs.
Page 283: Word Aligner In Manual Mode For Cpri
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 When using the byte deserializer, additional logic is required in the FPGA fabric to determine if the comma byte is received in the lower or upper byte of the word. The delay is dependent on the word in which the comma byte appears.
Page 284: How To Implement Cpri In Arria 10 Transceivers
You should be familiar with the Standard PCS and PMA architecture, PLL architecture, and the reset controller before implementing your CPRI protocol. 1. Instantiate the Arria 10 Transceiver Native PHY IP from the IP Catalog. Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
Page 285: Native Phy Ip Parameter Settings For Cpri
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 120. Connection Guidelines for a CPRI PHY Design tx_ready reset rx_ready Reset Controller pll_sel pll_locked pll_refclk PLL IP Core pll_cal_busy tx_serialclk0 rx_cdr_refclk tx_clkout Data Generator tx_serial_data tx_parallel_data Arria 10 Transceiver Native PHY...
Page 286 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Value warning Transceiver configuration rules CPRI (Auto) CPRI (Manual) PMA configuration rules basic Transceiver mode TX/RX Duplex Number of data channels 1-36 Data rate 1228.8 Mbps 2457.6 Mbps 3072 Mbps 4915.2 Mbps...
Page 287 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 207. RX PMA Parameters Parameter Value Number of CDR reference clocks Selected CDR reference clock Selected CDR reference clock frequency Select legal range defined by the Quartus Prime software...
Page 288 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameters Value RX rate match FIFO mode Disabled RX rate match insert / delete -ve pattern (hex) 0x00000000 RX rate match insert / delete +ve pattern (hex) 0x00000000 Enable rx_std_rmfifo_full port...
Page 289: Other Protocols
KR FEC PCS blocks. You can implement all other required logic for your specific application, such as standard or proprietary protocol multi-channel alignment, either in the FPGA fabric in soft IP or use Intel's 10GBASE-KR PHY IP core product as full solutions in the FPGA.
Page 290 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 121. Transceiver Channel Datapath and Clocking for Basic (Enhanced PCS) Configuration Transmitter PMA Transmitter Enhanced PCS FPGA Fabric 32-bit data PRBS Generator Generator tx_clkout Parallel Clock (322.265625 MHz) tx_pma_div_clkout...
Page 291 Basic (Enhanced PCS) or Basic with KR FEC Transceiver Configuration Rule. 1. Open the IP Catalog and select the Arria 10 Transceiver Native PHY IP. Refer to Select and Instantiate the PHY IP Core on page 33 for more details.
Page 292 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 123. Signals and Ports of Native PHY IP for Basic (Enhanced PCS) and Basic with KR FEC Configurations reconfig_reset tx_cal_busy NIOS Reconfiguration reconfig_clk rx_cal_busy Hard Calibration IP Registers reconfig_avmm...
Page 293 2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic with KR FEC This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values. Table 211.
Page 294 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Range (48) (49) GT transceiver channel: 1 Gbps to 25.8 Gbps Enable datapath and interface reconfiguration On / Off Enable simplified data interface On / Off Table 212. TX PMA Parameters...
Page 295 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Range Enable rx_pma_div_clkout port On / Off rx_pma_div_clkout division factor Disabled, 1, 2, 33, 40, 66 Enable rx_pma_clkslip port On / Off Enable rx_pma_qpipulldn port (QPI) On / Off...
Page 296 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Range Enable rx_enh_fifo_del port (10GBASE-R) On / Off Enable rx_enh_fifo_insert port (10GBASE-R) On / Off Enable rx_enh_fifo_rd_en port (Interlaken) On / Off Enable rx_enh_fifo_align_val port (Interlaken) On / Off...
Page 297 Generate parameter documentation file On / Off Related Information Using the Arria 10 Transceiver Native PHY IP Core on page 45 2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS In the Parameter Editor, use the following settings to enable low latency: 1.
Page 298 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 126. TX FIFO Basic Mode Operation tx_clkout (read side) tx_coreclk (write side) tx_parallel_data[63:0] 64’ d 0 64’ d 1 64’ d 2 64’ d 3 64’ d 4 64’ d 5 64’...
Page 299 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 assignments. Each TX channel has its own TX bit slip assignment and the bit slip amount is relative to the other TX channels. You can improve lane-to-lane skew by assigning TX bit slip ports with proper values.
Page 300: Using The Basic/Custom, Basic/Custom With Rate Match Configurations Of Standard Pcs
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS Use one of the following transceiver configuration rules to implement protocols such as SONET/SDH, SDI/HD, SATA, or your own custom protocol: •...
Page 301 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 131. Transceiver Channel Datapath and Clocking for Basic Configuration with Low Latency Enabled The clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits.
Page 302 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Note: • is asserted whenever there is a pattern match. rx_patterndetect • is asserted after the word aligner achieves synchronization. rx_syncstatus • is asserted to re-align and resynchronize. rx_std_wa_patternalign •...
Page 303 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 133. Manual Mode when the PCS-PMA Interface Width is 10 Bits = 10'h3BC and the word aligner pattern = 10'h3BC tx_parallel_data rx_std_wa_patternalign tx_parallel_data rx_parallel_data rx_patterndetect rx_syncstatus rx_std_wa_patternalign tx_parallel_data rx_parallel_data...
Page 304 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 The 8B/10B encoder and decoder add the following additional ports: • tx_datak • rx_datak • rx_errdetect • rx_disperr • rx_runningdisp 1. Set the RX word aligner mode to synchronous state machine.
Page 305 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 The RX bit slip feature is optional and may or may not be enabled. Figure 137. RX Bit Slip in 8-bit Mode = 8'hbc tx_parallel_data rx_std_bitslipboundarysel 01111 rx_bitslip tx_parallel_data rx_parallel_data Figure 138.
Page 306 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 141. RX Polarity Inversion rx_polinv tx_parallel_data 11111100001110111100 rx_parallel_data 11111100001... 00000011110001000011 11111100001110111100 rx_patterndetect rx_syncstatus 2.9.2.5. RX Bit Reversal The RX bit reversal feature can be enabled in low latency, basic, and basic rate match mode.
Page 307 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 1. Select basic (single width) in the RX rate match FIFO mode list. 2. Enter values for the following parameters. Parameter Value Description RX rate match insert/delete +ve 20 bits of data specified...
Page 308 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 The following figure shows the deletion of D5 when the upstream transmitter reference clock frequency is greater than the local receiver reference clock frequency. It asserts for one parallel clock cycle while the rx_std_rmfifo_full deletion takes place.
Page 309 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 The rate match FIFO can insert as many pairs of skip patterns into a cluster necessary to avoid the rate match FIFO from under running. The 10-bit skip pattern can appear on the MSByte, the LSByte, or both, of the 20-bit word.
Page 310 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 151. Rate Match FIFO Becoming Empty After Reading out the 20-Bit Word D5D6 tx_parallel_data[19:0] tx_parallel_data[9:0] rx_parallel_data[19:10] /K30.7/ rx_parallel_data[9:0] /K30.7/ rx_std_rmfifo_empty 2.9.2.9. 8B/10B Encoder and Decoder To enable the 8B/10B Encoder and the 8B/10B Decoder, select the Enable TX 8B/10B Encoder and Enable RX 8B/10B Decoder options on the Standard PCS tab in the IP Editor.
Page 311 RD– dataout[9:0] 2.9.2.11. How to Enable Low Latency in Basic In the Arria 10 Transceiver Native PHY IP Parameter Editor, use the following settings to enable low latency: 1. Select the Enable 'Standard PCS' low latency mode option. 2. Select either low_latency or register FIFO in the TX FIFO mode list.
Page 312 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Note: values in the following figures are based on the TX and RX rx_parallel_data bit reversal features being disabled. Figure 153. TX Bit Slip in 8-bit Mode = 8'hbc. = 5'b00001 (bit slip by 1 bit).
Page 313 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.9.2.14. TX Bit Reversal The TX bit reversal feature can be enabled in low latency, basic, and basic rate match mode. The word aligner is available in any mode. This feature is parameter-based, and creates no additional ports.
Page 314 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 159. Signals and Ports of Native PHY IP for Basic, Basic with Rate Match Configurations Arria 10 Transceiver Native PHY reconfig_reset Reconfiguration Nios Hard tx_cal_busy reconfig_clk Registers Calibration IP...
Page 315 2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match Configurations This section contains the recommended parameter values for this protocol. Refer to Using the Arria 10 Transceiver Native PHY IP Core for the full range of parameter values. Table 217.
Page 316 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Parameter Range TX local clock division factor 1, 2, 4, 8 Number of TX PLL clock inputs per channel 1, 2, 3, 4 Initial TX PLL clock input selection 0 (Depends on the Number of TX PLL clock...
Page 317 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Table 220. Standard PCS Parameters Parameter Range Standard PCS / PMA interface width 8, 10, 16, 20 FPGA fabric / Standard TX PCS interface width 8, 10, 16, 20, 32, 40...
Page 318 Enable Altera Debug Master Endpoint On/Off Table 222. Generation Options Parameters Parameter Range Generate parameter documentation file On/Off Related Information Using the Arria 10 Transceiver Native PHY IP Core on page 45 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 319: Design Considerations For Implementing Arria 10 Gt Channels
The serializer/deserializer in GT channels supports 64 bit and 128 bit serialization factors. 2.9.3.1. Transceiver PHY IP Arria 10 GT transceiver channels are implemented using the Native PHY IP with the Basic (Enhanced PCS) transceiver configuration rule. •...
Page 320 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 161. GT Channel Configuration Ch 5 Ch 4 CMU or CDR ATX PLL1 Ch 3 Ch 2 Ch 1 ATX PLL0 CMU or CDR Ch 0 When both the channels 0 and 1 are configured as GT channels, they are driven by the same ATX PLL and have to be configured to run at the same data rates.
Page 321 Transceiver Native PHY IP Parameters Settings for Basic (Enhanced PCS) and Basic with KR FEC for each input of the Arria 10 Transceiver Native PHY Parameter Editor as a starting point. Or, you can use the protocol presets described in Transceiver Native PHY Presets.
Page 322 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 162. Signals and Ports of the Native PHY for Basic (Enhanced PCS) Transceiver Configuration Rule for Data Rates Above 17.4 Gbps and FPGA Fabric / PCS Interface width of 128 bits...
Page 323 Prime software automatically uses the dedicated GT clocks instead of the x1 clock network. 2.9.3.5. Arria 10 GT Channel Usage All Arria 10 GT devices have a total of six GT transceiver channels to support 25.8 Gbps. Arria 10 GT devices have three transceiver banks that support up to two GT channels.
Page 324: How To Implement Pcs Direct Transceiver Configuration Rule
PCS Direct Transceiver Configuration Rule. 1. Open the IP Catalog and select Arria 10 Transceiver Native PHY IP. Refer to Select and Instantiate the PHY IP Core on page 33 for detailed steps.
Page 325: Simulating The Transceiver Native Phy Ip Core
Use simulation to verify the Native PHY transceiver functionality. The Quartus Prime software supports register transfer level (RTL) and gate-level simulation in both ModelSim - Intel FPGA Edition and third-party simulators. You run simulations using your Quartus Prime project files.
Page 326: Nativelink Simulation Flow
NativeLink—This flow simplifies simulation by allowing you to start a simulation from the Quartus Prime software. This flow automatically creates a simulation script and compiles design files, IP simulation model files, and Intel simulation library models. Note: The Quartus Prime Pro Edition software does not support NativeLink RTL simulation •...
Page 327 5. In the Tool name list, select your simulator. Note: ModelSim refers to ModelSim SE and PE. These simulators use the same commands as QuestaSim.ModelSim - Intel FPGA Edition refers to ModelSim - Intel FPGA Edition Starter Edition and ModelSim - Intel FPGA Edition Subscription Edition.
Page 328 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.10.1.2. How to Use NativeLink to Run a ModelSim RTL Simulation Figure 165. NativeLink Simulation Flow Diagram Specify EDA Simulator & Simulator Directory Run RTL Functional or Gate-Level Simulation Does...
Page 329 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Complete the following steps to run an RTL functional simulation: 1. Open your Quartus Prime project. 2. On the Tools menu, select Run Simulation Tool, then select RTL Simulation or Gate Level Simulation.
Page 330 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Figure 166. Using NativeLink with Third-Party Simulators Specify EDA Simulator & Simulator Directory Perform Functional Simulation Does Does Simulation Give Simulation Give Expected Results? Expected Results? Debug Design & Make RTL Changes...
Page 331: Scripting Ip Simulation
It also generates files for synthesis and simulation, including the .spd files necessary for the ip-setup-simulation utility. The Intel Quartus Prime software provides utilities to help you generate and update IP simulation scripts. You can use the ip-setup-simulation utility to generate a combined simulator setup script, for all Intel FPGA IP in your design, for each supported simulator.
Page 332: Custom Simulation Flow
2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 2.10.3. Custom Simulation Flow The custom simulation flow allows you to customize the simulation process for more complex simulation requirements. This flow allows you to control the following aspects of your design: •...
Page 333 Simulation Give Expected Results? Simulation Complete 2.10.3.1. How to Use the Simulation Library Compiler The Simulation Library Compiler compiles Intel simulation libraries for supported simulation tools, and saves the simulation files in the output directory you specify. ® ® Intel...
Page 334 UG-01143 | 2018.06.15 Note: Because the ModelSim - Intel FPGA Edition software provides precompiled simulation libraries, you do not have to compile simulation libraries if you are using the software. Complete the following steps to compile the simulation model libraries using the Simulation Library Compiler: 1.
Page 335: Implementing Protocols In Intel Arria 10 Transceivers Revision History
Run this script at the command line using quartus_sh –t (NCSim) ncsim_setup.sh <script>. Any testbench you specify with NativeLink is included in this script. 2.11. Implementing Protocols in Intel Arria 10 Transceivers Revision History Document Changes Version 2018.06.15 Made the following changes: •...
Page 336 Added further description to the signal in the "Optional Control and Status rx_channelaligned Signals—Soft IP Implementation" table. Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section: • Added "Synchronous to " for in the clock rx_clkout rx_std_wa_patternalign[<n>-1:0]...
Page 337 Replaced the "Design Considerations for Data Rates above 17.4 Gbps Using Arria 10 GT Channels” section. • Changed the title from "Design Considerations for Data Rates above 17.4 Gbps Using Arria 10 GT Channels” to "Design Considerations for implementing Arria 10 GT Channels”. •...
Page 338 Updated the “PMA configuration rules” value in the General and Datapath Options table in the General and Datapath Parameters section. • Removed footnote and added "Hard IP for PCI Express to Native PHY IP" in the “Arria 10 Transceiver Protocols and PHY IP Support” table. •...
Page 339 Updated description of parameter “PCS TX channel bonding master” in the “Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA” table. • Added table “Parameter Settings for Arria 10 fPLL IP in PIPE Gen1, Gen2, Gen3 modes” in the “fPLL IP Parameter Settings for PIPE” section. continued...
Page 340 Changes Version • Added table “Parameters for Arria 10 ATX PLL IP in PIPE Gen1, Gen2, Gen3 modes” in the “ATX PLL IP Parameter Settings for PIPE” section. • Updated description of port pipe_tx_elecidle in the “Ports for Arria 10 Transceiver Native PHY in PIPE Mode”...
Page 341 "XAUI PHY Timing Analyzer SDC Constraints" set_max_skew section. Made the following changes to the Using the Arria 10 Transceiver Native PHY IP Core section: • Updated the figure for Transceiver Native PHY IP Core Parameter Editor. •...
Page 342 2. Implementing Protocols in Arria 10 Transceivers UG-01143 | 2018.06.15 Document Changes Version Made the following changes to the 10GBASE-R section: • Added a figure description to the "Signals and Ports of Native PHY IP Core for the 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC" figure.
Page 343 • Updated the figures in How to Place Channels for PIPE Configurations. • Updated the Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - TX PMA table. • Updated the clock domains in Signals and Ports of Native PHY IP for PIPE figure.
Page 344 UG-01143 | 2018.06.15 Document Changes Version Made the following changes to the Arria 10 Transceiver Protocols and PHY IP Support section: • Updated table "Arria 10 Transceiver Protocols and PHY IP Support" — Removed SFIS and 10G SDI from the table.
Page 345 • Removed the introductory paragraph from the Design Example section. • Removed the 1588 FIFO block from the "Top Level Modules of the 1G/10GbE PHY Intel FPGA IP Core Function" figure. • Updated all values for ALMs, ALUTs, Registers, and M20K in the "1G/10GbE PHY Performance and Resource Utilization"...
Page 346 — Updated the "General and Datapath Options Parameters", "TX PMA Parameters", "RX PMA Parameters", and "Standard PCS Parameters" tables. • Design Considerations for Data Rates Above 17.4 Gbps Using Arria 10 GT Channels — Updated the maximum data rate for GT channels to 25.4 Gbps. — Added information about PCS Direct mode.
Page 347: Plls And Clock Networks
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 348 3. PLLs and Clock Networks UG-01143 | 2018.06.15 Figure 168. Arria 10 PLLs and Clock Networks Transceiver x1 Clock Lines x6 Clock Lines xN Clock Lines Bank Local CGB fPLL CDR/CMU Local CGB Master Local CGB Transceiver Bank Local CGB...
Page 349: Plls
Using PLLs and Clock Networks on page 398 Information on how to use PLL IP to implement bonded and non-bonded transceiver designs. 3.1. PLLs Table 228. Transmit PLLs in Arria 10 Devices PLL Type Characteristics Advanced Transmit (ATX) PLL • Best jitter performance •...
Page 350: Atx Pll
For two ATX PLLs providing the serial clock for PCIe/PIPE Gen3, they must be placed 4 ATX PLL apart (skip 3). Note: If these spacing rules are violated, Intel Quartus Prime issues a critical warning. When two ATX PLLs are being used, and you meet the following two conditions in your applications: •...
Page 351 Sourcing reference clock from a cascaded PLL output, global clock or core clock network introduces additional jitter to the ATX PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details.
Page 352 OTN and SDI protocols. The delta sigma modulator is used in fractional mode. It modulates the M counter divide value over time so that the PLL can perform fractional frequency synthesis. In fractional mode, the M value is as follows: . ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 353 4. Generate the ATX PLL IP and control the reconfiguration streamer using the AVMM master. Related Information • Calibration on page 567 • How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock? ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 354 UG-01143 | 2018.06.15 3.1.2.1. Instantiating the ATX PLL IP Core The Arria 10 transceiver ATX PLL IP core provides access to the ATX PLLs in the hardware. One instance of the PLL IP core represents one ATX PLL in the hardware.
Page 355 You can enable both the GX clock output port and the GT clock output port. However, only one port can be in operation at any given time. You can switch between the two ports using PLL reconfiguration. (52) The fPLL signals should only be used with the Intel external soft lock fref clklow detection logic. (53) Manually enable the MCGB for bonding applications.
Page 356 Enables soft registers for reading status signals and writing control signals on the PLL interface through the embedded debug logic. Configuration file prefix Enter the prefix name for the configuration files to be generated. continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 357 Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY Reset Controller pll_powerdown output if using this Intel FPGA IP). pll_refclk0 Input Reference clock input port 0. There are a total of five reference clock input ports.
Page 358 Used for channel bonding, and represents the x6/xN clock network. mcgb_serial_clk Output High speed serial clock output for x6/xN non-bonded configurations. continued... (54) Connect this clock to in PCIe applications. hclk ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 359: Fpll
Refer to the Avalon specification for more details about these ports. • Intel Arria 10 Device Datasheet Refer to the Intel Arria 10 Device Datasheet for more details about the PLL output frequency range. • Reconfiguration Interface and Dynamic Reconfiguration on page 502 •...
Page 360 Sourcing reference clock from a cascaded PLL output, global clock or core clock network introduces additional jitter to the fPLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details.
Page 361 The dynamic phase shift block allows you to adjust the phase of the C counters in user mode. In fractional mode, dynamic phase shift is only available for the C counters. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 362 Arria 10 PLL reference clock? 3.1.3.1. Instantiating the fPLL IP Core The fPLL IP core for Arria 10 transceivers provides access to fPLLs in hardware. One instance of the fPLL IP core represents one fPLL in the hardware. 1. Open the Quartus Prime software.
Page 363 Enable PCIe clock switch interface On/Off Enables the control signals used for PCIe clock switch circuitry. continued... (56) The fPLL signals should only be used with the Intel external soft lock fref clklow detection logic. ® ® Intel Arria...
Page 364 PLL. Generate MIF (Memory Initialize On/Off Generates a MIF file that contains the current configuration. File) Use this option for reconfiguration purposes in order to switch between different PLL configurations. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 365 Resets the PLL when asserted high. Needs to be connected to a dynamically controlled signal (the Transceiver PHY Reset Controller pll_powerdown output if using this Intel FPGA IP). pll_refclk0 input Reference clock input port 0. There are five reference clock input ports.
Page 366 Used for channel bonding, and represents the x6/xN clock network. mcgb_serial_clk output High speed serial clock output for x6/xN non-bonded configurations. pcie_sw[1:0] input Asynchronous 2-bit rate switch control input used for PCIe protocol implementation. continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 367 • Calibration on page 29 • Reconfiguration Interface and Dynamic Reconfiguration on page 502 (57) The fPLL signals should only be used with the Intel external soft lock fref clklow detection logic. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 368: Cmu Pll
The input reference clock is a differential signal. For protocol jitter compliance at data rates > 10 Gbps, Intel recommends using the dedicated reference clock pin in the same triplet with the CMU PLL as the input reference clock source.The input reference clock must be stable and free-running at...
Page 369 There is a pre-divider to lower the frequency in case the frequency is too high. Related Information • Calibration on page 567 • IntelArria 10 Device Datasheet ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 370 UG-01143 | 2018.06.15 3.1.4.1. Instantiating CMU PLL IP Core The CMU PLL IP core for Arria 10 transceivers provides access to the CMU PLLs in hardware. One instance of the CMU PLL IP core represents one CMU PLL in hardware.
Page 371 The number of reference clock ports available depends on the Number of PLL reference clocks parameter. input Reference clock input port 1. pll_refclk1 input Reference clock input port 2. pll_refclk2 continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 372: Input Reference Clock Sources
The transmitter PLL and the clock data recovery (CDR) block need an input reference clock source to generate the clocks required for transceiver operation. The input reference clock must be stable and free-running at device power-up for proper PLL calibrations. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 373 (2) Dedicated refclk pin can be used as an input reference clock source only for ATX or fPLL or to the reference clock network. Reference clock network can then drive the CMU PLL. (3) The output of another PLL can be used as an input reference clock source during PLL cascading. Arria 10 transceivers support fPLL to fPLL cascading. Note: •...
Page 374: Dedicated Reference Clock Pins
Dedicated refclk Pin 3.2.2. Receiver Input Pins Receiver input pins can be used as an input reference clock source to transceiver PLLs. However, they cannot be used to drive core fabric. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 375: Pll Cascading As An Input Reference Clock Source
PLL. PLL cascading can generate frequency outputs not normally possible with a single PLL solution. The transceiver in Arria 10 devices support fPLL to fPLL cascading, with only maximum two fPLLs allowed in the cascading chain. ATX PLL to fPLL cascading is available to OTN and SDI protocols only.
Page 376: X1 Clock Lines
The x1 clock lines can be driven by the ATX PLL, fPLL, or by either one of the two channel PLLs (channel 1 and 4 when used as a CMU PLL) within a transceiver bank. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 377: X6 Clock Lines
There are two x6 clock lines per transceiver bank, one for each master CGB. Any channel within a transceiver bank can be driven by the x6 clock lines. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 378 The x6 clock lines also drive the xN clock lines which route the clocks to the neighboring transceiver banks. Figure 176. x6 Clock Lines Network Ch 5 Bottom Ch 4 CMU or CDR Master Ch 3 Ch 2 Ch 1 CMU or CDR Master Ch 0 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 379: Xn Clock Lines
CGB is used, and the local CGB within each channel is bypassed. For non-bonded configurations, the master CGB provides a high speed serial clock output to each channel. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 380 The maximum data rate supported by the xN clock network while driving channels in either the bonded or non-bonded mode depends on the voltage used to drive the transceiver banks. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 381: Gt Clock Lines
IntelArria 10 Device Datasheet 3.3.4. GT Clock Lines GT clock lines are dedicated clock lines available only in Arria 10 GT devices. Each ATX PLL has two dedicated GT clock lines that connect the PLL directly to the transceiver channels within a transceiver bank. The top ATX PLL drives channels 3 and 4, and the bottom ATX PLL drives channels 0 and 1.
Page 382 3. PLLs and Clock Networks UG-01143 | 2018.06.15 Figure 178. GT Clock Lines Ch 5 Ch 4 CMU or CDR ATX PLL1 Ch 3 Ch 2 Ch 1 ATX PLL0 CMU or CDR Ch 0 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 383: Clock Generation Block
3. PLLs and Clock Networks UG-01143 | 2018.06.15 3.4. Clock Generation Block In Arria 10 devices, there are two types of clock generation blocks (CGBs) • Local clock generation block (local CGB) • Master clock generation block (master CGB) Each transmitter channel has a local clock generation block (CGB). For non-bonded channel configurations, the serial clock generated by the transmit PLL drives the local CGB of each channel.
Page 384: Fpga Fabric-Transceiver Interface Clocking
The FPGA fabric-transceiver interface consists of clock signals from the FPGA fabric into the transceiver and clock signals from the transceiver into the FPGA fabric. These clock signals use the global (GCLK), regional (RCLK), and periphery (PCLK) clock ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 385 Serial Clock Parallel and Serial Clocks Serial Clock tx_clkout (from CGB) tx_pma_div_clkout Deserializer CDR Recovered Clock rx_clkout rx_pma_div_clkout The divided versions of the are available as tx_clkout rx_clkout , respectively. tx_pma_div_clkout rx_pma_div_clkout ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 386: Transmitter Data Path Interface Clocking
TX phase compensation FIFO. The clock used to clock the read side of the TX phase compensation FIFO is also forwarded to the FPGA fabric to provide an interface between the FPGA fabric and the transceiver. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 387: Receiver Data Path Interface Clocking
• Recovered parallel clock from the CDR in the PMA. • Parallel clock from the clock divider used by the transmitter PCS (if enabled) for that channel. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 388 Quartus Prime selected receiver datapath interface clock • User-selected receiver datapath interface clock Related Information Unused or Idle Clock Line Requirements on page 389 For more information about unused or idle transceiver clock lines in design. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 389: Unused/Idle Clock Line Requirements
In order to prevent the performance degradation, for idle transceiver RX channels, recompile designs with Intel Quartus Prime version 16.1 or later with the assignment described in the link shown below. The CLKUSR pin must be assigned a 100-125 MHz clock.
Page 390 Bonding has the following disadvantages: • The maximum data rate is restricted based on the transceiver supply voltage. Refer to Arria 10 Device Data Sheet. • The maximum channel span is limited to two transceiver banks above and below the bank containing the transmit PLL.
Page 391: Pma And Pcs Bonding
For PMA bonding, either x6/xN or PLL feedback compensation bonding is used. For PCS bonding, some of the PCS control signals within the bonded group are skew aligned using dedicated hardware inside the PCS. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 392: Selecting Channel Bonding Schemes
Swapping of channels, when doing pin assignments, leads to errors. 3.9.3. Selecting Channel Bonding Schemes In Arria 10 devices, select PMA and PCS bonding for bonded protocols that are explicitly supported by the hard PCS blocks. For example, PCI Express, SFI-S, and 40GBASE-KR.
Page 393: Skew Calculations
3.10. PLL Feedback and Cascading Clock Network The PLL feedback and cascading clock network spans the entire side of the device, and is used for PLL feedback compensation bonding and PLL cascading. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 394 Connection (2) fbclk ATX PLL 0 refclk fbclk Master CGB0 Bidirectional Tristate Buffer Legend refclk Lines PLL Cascading fbclk Lines PLL Feedback Compensation Bonding C, M, and CGB Outputs ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 395 For PLL cascading, connections (1) and (3) are used to connect the output of one PLL to the reference clock input of another PLL. The transceivers in Arria 10 devices support fPLL to fPLL, and ATX PLL to fPLL (via dedicated ATX PLL to fPLL cascade path) cascading. Only maximum two PLLs allowed in the cascading chain.
Page 396 L Counter C Counters fPLL M Counter Phase Multiplexer Figure 188. Integer and Phase Aligned refclk N Counter L Counter C Counters Phase fPLL M Counter Multiplexer PLL Feedback Clock Network ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 397 You must recalibrate the fPLL when you enable the phase alignment option. 1. Modify the fPLL IP to enable fPLL reconfiguration • Under the Dynamic Reconfiguration Tab, turn ON Enable dynamic reconfiguration. 2. Create logics in the core to perform following steps: ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 398: Using Plls And Clock Networks
408 3.11. Using PLLs and Clock Networks In Arria 10 devices, PLLs are not integrated in the Native PHY IP core. You must instantiate the PLL IP cores separately. Unlike in previous device families, PLL merging is no longer performed by the Quartus Prime software. This gives you more control, transparency, and flexibility in the design process.
Page 399 PLL instance. It is also possible to use more than two PLL IP cores and have different PLLs driving different channels. If some channels are running at different data rates, then you need different PLLs driving different channels. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 400 For the CMU PLL IP core, specify the reference clock and the data rate. No special configuration rule is required. 3. Configure the Native PHY IP core using the IP Parameter Editor ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 401 TX Channel TX Channel TX Channel TX Channel TX Channel TX Channel TX Channel Legend: TX channels placed in the same transceiver bank. TX channels placed in the adjacent transceiver bank. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 402 Each port corresponds to the input of the local CGB of the transceiver channel. • As shown in the figure above, connect the output port of mcgb_serial_clk the PLL IP core to the 10 ports of the Native PHY IP tx_serial_clk input core. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 403: Bonded Configurations
In bonded configurations, the transceiver clock skew between the channels is minimized. Use bonded configurations for channel bonding to implement protocols such as PCIe and XAUI. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 404 Set the number of channels required by your design. In this example, the number of channels is set to 10. 4. Create a top level wrapper to connect the PLL IP core to Native PHY IP core. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 405 Intel Quartus Prime software fitter errors. • Connect the PLL IP core to the PHY IP core by duplicating the output of the PLL[5:0] for the number of channels. For 10 channels, the Verilog syntax for the input port connection is .tx_bonding_clocks...
Page 406 362 for detailed steps. Because the CMU PLL cannot drive the master CGB, only the ATX PLL or fPLL can be used for feedback compensation bonding. 2. Configure the PLL IP core using the IP Parameter Editor. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 407 For fPLL, Read-Modify-Write 0x1 to offset address 0x126[0] of the fPLL. 2. Recalibrate the PLL. 3. After recalibration completes, ensure the PLL achieves lock. Dynamic reconfigure the PLL to change the feedback to master CGB. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 408: Implementing Pll Cascading
The transceivers in Arria 10 devices support fPLL to fPLL cascading. For OTN and SDI applications, there is a dedicated clock path for cascading ATX PLL to fPLL in Arria 10 production silicon. Only maximum two PLLs are allowed in the cascading chain.
Page 409: Mix And Match Example
576 3.11.4. Mix and Match Example In the Arria 10 transceiver architecture, the separate Native PHY IP core and the PLL IP core scheme allows great flexibility. It is easy to share PLLs and reconfigure data rates. The following design example illustrates PLL sharing and both bonded and non- bonded clocking configurations.
Page 410 PLL Instances In this example, two ATX PLL instances and five fPLL instances are used. Choose an appropriate reference clock for each PLL instance. The IP Catalog lists the available PLLs. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 411 Transceiver PLL instance 6: ATX PLL with output clock frequency of 4 GHz — Enable Master CGB and bonding output clocks. — Select Enable PCIe clock switch interface option. — Set Number of Auxiliary MCGB Clock Input ports to 1. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 412 • PCIe Gen3 with a bonded group of 8 channels — Set the PCIe PIPE Gen3x8 preset from the Arria 10 Transceiver Native PHY IP core GUI. — Under TX Bonding options, set the PCS TX channel bonding master to channel 5.
Page 413: Timing Closure Recommendations
3.11.5. Timing Closure Recommendations Register mode is harder to close timing in Arria 10 devices. Intel recommends using negative edge capture on the RX side for periphery to core transfers greater than 240 MHz. To be specific, capture on a negative edge clock in the core and then immediately transfer to a positive edge clock.
Page 414: Plls And Clock Networks Revision History
Added note "Sourcing reference clock from a cascaded PLL output, global clock or core clock network will introduce additional jitter to transmit PLL output. Refer to KDB "How do I compensate for the jitter of PLL cascading or non-dedicated clock path for Arria 10 PLL reference clock?" for more details."...
Page 415 Added a new section for Channel Bonding describing PMA bonding, PMA and PCS bonding in detail. • Removed xN Clock Network Data Rate Restrictions table. • Updated chapter to indicate Arria 10 Transceivers support fPLL to fPLL, fPLL to ATX PLL, and fPLL to CMU PLL cascading. • Updated Using PLLs and Clock Networks section —...
Page 416: Resetting Transceiver Channels
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 417: Transceiver Phy Implementation
(feeding it to the core), you must instantiate altera_a10_xcvr_clock_module altera_a10_xcvr_clock_module reset_clock (.clk_in(mgmt_clk)); For more information about the CLKUSR pin, refer to the Arria 10 Pin Connection Guidelines. (59) There is only one centralized TRS instantiated for one or more Native PHY.
Page 418: How Do I Reset
You reset a transceiver PHY or PLL by integrating a reset controller in your system design to initialize the PCS and PMA blocks. You can save time by using the Intel- provided Transceiver PHY Reset Controller IP core, or you can implement your own reset controller that follows the recommended reset sequence.
Page 419 4. Resetting Transceiver Channels UG-01143 | 2018.06.15 Figure 200. Arria 10 Default Settings Preset ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 420 The following steps detail the transmitter reset sequence during device operation. The step numbers correspond to the numbers in the following figure. 1. Perform the following steps: ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 421 = 70 μs Note: (1) The Arria 10 Default setting presets tx_digitalreset to 70 μs. (2) Area in gray is don’t care logic state. Related Information Arria 10 Device Datasheet 4.3.1.1.2. Resetting the Receiver During Device Operation Follow this reset sequence to reset the analog or digital blocks of the receiver at any point during the device operation.
Page 422 Use the following control settings to set the CDR lock mode: Table 245. Control Settings for the CDR in Manual Lock Mode rx_set_locktoref rx_set_locktodata CDR Lock Mode Automatic Manual-RX CDR LTR Manual-RX CDR LTD ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 423 6. If you are using the Transceiver PHY Reset Controller, the status signal rx_ready gets asserted after the signal is deasserted. This indicates rx_digitalreset that the receiver is now ready to receive data with the CDR in manual mode. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 424 (minimum of 70 μs) duration after is deasserted. tx_analogreset 5. Deassert after deasserting rx_analogreset tx_analogreset 6. Ensure is asserted for t (minimum of 4 μs) before rx_is_lockedtodata deasserting rx_digitalreset ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 425 70 μs after deasserting to monitor the tx_analogreset pll_locked signal. 5. Deassert after goes high. The tx_digitalreset pll_locked signal must stay asserted for a minimum tx_digitalreset tx_digitalreset duration after is deasserted. tx_analogreset ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 426 = 70 μs Note: (1) The Arria 10 Default setting presets ttx_digitalreset to 70 μs. (2) Area in gray is don’t care zone. RX Channel The numbers in this list correspond to the numbers in the following figure.
Page 427: Model 2: Acknowledgment Model
Native PHY IP core: • Enable the port in the TX PMA tx_analog_reset_ack Figure 208. Enabling the tx_analog_reset_ack Port • Enable the port in the RX PMA rx_analog_reset_ack Figure 209. Enabling the rx_analog_reset_ack Port ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 428 Figure 210. Transmitter Reset Sequence During Device Operation Device Power Up pll_cal_busy tx_cal_busy tx_analogreset tx_analogreset_ack pll_powerdown pll_locked tx_digitalreset tx_digitalreset Note: (1) Area in gray is don’t care logic state. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 429 2. Wait for to go high, to ensure successful assertion of tx_analogreset_ack goes high when TRS has successfully tx_analogreset tx_analogreset_ack completed the reset request for assertion. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 430 4.3.2.1.4. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model The numbers in this list correspond to the numbers in the "Dynamic Reconfiguration of Receiver Channel During Device Operation" figure below. 1. Assert while is low. rx_analogreset rx_digitalreset rx_cal_busy ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 431 1 μs or more, apply the reset sequence from the "Reset Sequence Timing Diagram for Receiver when CDR is in Manual Lock Mode" figure below. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 432: Transceiver Blocks Affected By Reset And Powerdown Signals
Block CMU PLL ATX PLL fPLL Receiver Standard PCS Receiver Enhanced PCS Receiver PMA Receiver PCIe Gen3 PCS Transmitter Standard PCS Transmitter Enhanced PCS Transmitter PMA Transmitter PCIe Gen3 PCS ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 433: Using The Transceiver Phy Reset Controller
The following figure illustrates the typical use of the Transceiver PHY Reset Controller in a design that includes a transceiver PHY instance and the transmit PLL. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 434 Figure 215. Transceiver PHY Reset Controller System Diagram Status Signals tx_ready rx_ready tx_analogreset Transceiver PHY Instance tx_digitalreset Reset Controller rx_analogreset Transmitter Transmitter clock rx_digitalreset (user-coded or Intel IP) reset rx_cal_busy Receiver Receiver rx_is_lockedtoref rx_is_lockedtodata tx_analogreset_ack rx_analogreset_ack pll_tx_cal_busy tx_cal_busy (1) pll_cal_busy (1) Transmit Transceiver Reset Sequencer Inferred Block...
Page 435: Parameterizing The Transceiver Phy Reset Controller Ip
When Off, the reset input is not synchronized. Use fast reset for simulation On /Off When On, the Transceiver PHY Reset Controller uses reduced reset counters for simulation. continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 436 The value is rounded up to the nearest clock cycle. Note: Model 1 requires this to be set to 70 µs. Select the Arria 10 Default Settings preset. tx_digitalreset duration Specifies the time in ns to continue to assert the...
Page 437: Transceiver Phy Reset Controller Interfaces
The default value is 40 ns. Note: Model 1 requires this to be set to 70 µs. Select the Arria 10 Default Settings preset. rx_digitalreset duration Specifies the time in ns to continue to assert the...
Page 438 ANDed together internally to provide a single status signal. Input Asynchronous This optional signal places tx_manual[<n>-1:0] tx_digitalreset controller under automatic or manual control. When asserted, the associated controller tx_digitalreset continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 439 Digital reset for RX. The width of this signal depends rx_digitalreset[<n> Transceiver PHY Reset on the number of channels. This signal is asserted -1:0] Controller input clock. when any of the following conditions is true: continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 440 If three channels are instantiated with only one TX PLL and with a separate TX reset sequence per channel, the field is 3-bits wide. In this case, pll_select should be set to 0 since there is only one TX PLL available. pll_select ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 441: Transceiver Phy Reset Controller Resource Utilization
You must ensure a stable reference clock is present at the PLL transmitter before releasing pll_powerdown 4.5.1. User-Coded Reset Controller Signals Refer to the signals in the following figure and table for implementation of a user- coded reset controller. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 442: Combining Status Or Pll Lock Signals
(LTR) mode. This signal may toggle or be deasserted when the CDR is in LTD mode. 4.6. Combining Status or PLL Lock Signals You can combine multiple PHY status signals before feeding into the reset controller as shown below. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 443: Timing Constraints For Bonded Pcs And Pma Channels
PMA Bonding or for RX PCS channels. Note: If the design is not able to meet the maximum skew tolerance requirement with a positive margin, Intel recommends reassigning the channels locations that are not adjacent to the PCIe Hard IP block. ®...
Page 444 In the above example, you must make the following substitutions: • <IP_INSTANCE_NAME>—substitute the name of your reset controller IP instance or PHY IP instance • <½ coreclk period in ps>—substitute half of the clock period of your design in picoseconds ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 445: Resetting Transceiver Channels Revision History
Made the following change: • Added a note "If the design is not able to meet the maximum skew tolerance requirement with a positive margin, Intel recommends reassigning the channels locations that are not adjacent to the PCIe Hard IP block." 2016.05.02 Made the following changes •...
Page 446 Updated the "Resetting the Receiver During Device Operation" procedure and associated figure. • Updated the "Reset Sequence Timing Diagram for Transceiver when CDR is in Manual Lock Mode" figure. 2013.12.02 Initial release. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 447: Arria 10 Transceiver Phy Architecture
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 448: Transmitter Buffer
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 222. Serializer Block The serializer block sends out the least significant bit (LSB) of the input data first. Serial Parallel Data Serializer Data Serial Parallel Clock Clock 5.1.1.2. Transmitter Buffer The transmitter buffer includes the following circuitry: •...
Page 449 To improve performance, the Arria 10 transmitter uses a new architecture in the output buffer—High Speed Differential I/O. You should select "High Speed Differential I/O" for I/O standard of Arria 10 transmitter pin in Quartus Prime Assignment Editor or QSF file.
Page 450: Receiver
You can set pre-emphasis taps through the Quartus Assignment Editor, the Avalon-MM registers, and the QSF settings. Related Information For more information, refer to Arria 10 Pre-Emphasis and Output Swing Settings 5.1.1.2.4. Power Distribution Network (PDN) induced Inter-Symbol Interference (ISI) compensation Arria 10 Transmitter driver includes a compensation circuitry to reduce PDN induced ISI jitter.
Page 451: Receiver Buffer
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 225. Receiver PMA Block Diagram Receiver PMA Serial Serial Parallel Parallel Data Receiver Serial Data Data Data Receiver to FPGA Core Receiver Differential Input Deserializer Buffer Data Serial Clock Parallel Clock 5.1.2.1.
Page 452 AC gain circuitry provides amplification to the high-frequency spectrum gain of the incoming signal. Arria 10 transceivers support dual mode CTLE. High Gain Mode High gain mode supports data rate up to 17.4 Gbps. This mode provides both AC and DC gain.
Page 453 (dB) Frequency Note: Final equalization curves will be available in the Arria 10 device datasheet. High Data Rate Mode High Data Rate Mode is a low power mode that supports data rates up to 25.8 Gbps. It is the default mode if none of the modes are selected in the Quartus Assignment Editor or Quartus Settings File (.qsf).
Page 454 Arria 10 Register Map 5.1.2.1.5. Variable Gain Amplifier (VGA) Arria 10 channels have a variable gain amplifier to optimize the signal amplitude prior to the CDR sampling. VGA can only be operated in manual mode. VGA gain can be selected through Quartus Assignment Editor or Quartus Setting File (qsf) or the Avalon MM register.
Page 455 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 The DFE advantage over CTLE is improved Signal to Noise Ratio (SNR). DFE amplifies the power of the high frequency components without amplifying the noise power. Figure 229. Signal ISI ISI+...
Page 456 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 230. Channel Pulse Response Signal at the Region of Influence Channel Input for Fixed Taps Signal at the Transmission Medium Channel Output 1 UI Note: The pulse at the output of the channel shows a long decaying tail. Frequency- dependent losses and quality degradation affects other signals.
Page 457 Assignment Editor. Use this method to dynamically set values and hence avoid re-compilation. Refer to Arria 10 Transceiver Register Map for more details on AVMM interface and to perform dynamic read/write. Method 2 - Using AVMM Interface 1.
Page 458 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Refer to Arria 10 Register Map for details on the specific registers that set the CTLE gain values/DFE taps. b. For dynamically changing DFE and CTLE Adaptation modes, refer to CTLE Settings in Triggered Adaptation Mode, Arria 10 Register Map and Arria 10 DFE Adaptation Tool for the list of adaptation registers.
Page 459 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.1.2.2.2. Lock-to-Data Mode During normal operation, the CDR must be in LTD mode to recover the clock from the incoming serial data. In LTD mode, the PD in the CDR tracks the incoming serial data at the receiver input.
Page 460: Loopback
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.1.2.3. Deserializer The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes the data using the low-speed parallel recovered clock. The deserializer forwards the deserialized data to the receiver PCS or FPGA fabric, and sends out the LSB of the input data first.
Page 461: Arria 10 Enhanced Pcs Architecture
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 234. Reverse Serial Loopback Path/Pre CDR The reverse serial loopback path sets the transmitter buffer to transmit data fed directly from the VGA output. Adjusting the RX CTLE, and RX VGA settings has an effect on the serial data that goes through the diagnostic loopback path.
Page 462: Transmitter Datapath
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 236. Enhanced PCS Datapath Diagram Transmitter PMA Transmitter Enhanced PCS FPGA Fabric Data & Control PRBS Generator Generator Parallel Clock tx_clkout tx_pma_div_clkout Receiver PMA Receiver Enhanced PCS rx_pma_div_clkout Data &...
Page 463 FIFO output. Note: Intel recommends that you implement a soft FIFO in the FPGA fabric with a minimum of 32 words under the following conditions: • When the Enhanced PCS TX FIFO is set to register mode.
Page 464 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.2.1.2. Interlaken Frame Generator The Interlaken frame generator block takes the data from the TX FIFO and encapsulates the payload and burst/idle control words from the FPGA fabric with the framing layer’s control words (synchronization word, scrambler state word, skip word, and diagnostic word) to form a metaframe.
Page 465 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 238. Interlaken CRC-32 Generator The Interlaken CRC-32 generator implements the Interlaken protocol. Interlaken Metaframes with Embedded CRC-32 From the Interlaken Frame Generator CRC-32 Code to Scrambler Generator Metaframe Payload Payload...
Page 466 The PRBS generator in Arria 10 devices is a shared hardened block between the Standard and Enhanced datapaths through the PCS instead of being two unique instances: one for Standard PCS and one for the Enhanced PCS.
Page 467 TX and RX tests in the 10G Ethernet mode. You can use the Arria 10 Pseudo Random Pattern (PRP) generator in the scrambler to generate random data pattern and seed that the scrambler can use.
Page 468 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.2.1.6. Scrambler The scrambler randomizes data to create transitions to DC-balance the signal and help CDR circuits. The scrambler uses a x +1 polynomial and supports both synchronous scrambling used for Interlaken and asynchronous (also called self- synchronized) scrambling used for the 10GBASE-R protocol.
Page 469 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.2.1.7. Interlaken Disparity Generator The Interlaken disparity generator block is in accordance with the Interlaken protocol specification and provides a DC-balanced data output. The Interlaken protocol solves the unbounded baseline wander, or DC imbalance, of the 64B/66B coding scheme used in 10Gb Ethernet by inverting the transmitted data.
Page 470 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Most data transmission systems, such as Ethernet, have minimum requirements for the bit error rate (BER). However, due to channel distortion or noise in the channel, the required BER may not be achievable. In these cases, adding a forward error control correction can improve the BER performance of the system.
Page 471: Receiver Datapath
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 KR FEC TX Gearbox The KR FEC TX gearbox converts 65-bit input words to 64-bit output words to interface the KR FEC encoder with the PMA. This gearbox is different from the TX gearbox used in the Enhanced PCS.
Page 472 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.2.2.2. Block Synchronizer The block synchronizer determines the block boundary of a 66-bit word in the case of the 10GBASE-R protocol or a 67-bit word in the case of the Interlaken protocol. The incoming data stream is slipped one bit at a time until a valid synchronization header (bits 65 and 66) is detected in the received data stream.
Page 473 The PRBS checker in Arria 10 devices is a shared hardened block between the Standard and Enhanced datapaths. Hence, there is only one set of control signals and registers for this feature.
Page 474 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 The PRBS checker has the following control and status signals available to the FPGA fabric: • —Indicates the PRBS sequence has completed one full cycle. It rx_prbs_done stays high until you reset it with rx_prbs_err_clr •...
Page 475 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.2.2.8. 10GBASE-R Bit-Error Rate (BER) Checker The 10GBASE-R BER checker block is designed in accordance with the 10GBASE-R protocol specification as described in IEEE 802.3-2008 clause-49. After block lock synchronization is achieved, the BER checker starts to count the number of invalid synchronization headers within a 125-μs period.
Page 476 FIFO output. The RX FIFO in register mode has one register stage or one parallel clock latency. Note: Intel recommends that you implement a soft FIFO in the FPGA fabric with minimum of 32 words under the following conditions: •...
Page 477 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 248. RX FIFO as Interlaken Deskew FIFO FPGA Fabric Interface rx_enh_fifo_align_clr rx_enh_fifo_rd_en User RX FIFO rx_enh_fifo_pempty Deskew rx_enh_fifo_pfull 5.2.2.10.4. 10GBASE-R Mode In 10GBASE-R mode, the RX FIFO operates as a clock compensation FIFO. When the block synchronizer achieves block lock, data is sent through the FIFO.
Page 478 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 249. IDLE Word Deletion This figure shows the deletion of IDLE words from the receiver data stream. Before Deletion rx_parallel_data[79:0] 00000000000004ADh 00000000000004AEh 0707070707FD0000h 000000FB07070707h After Deletion rx_parallel_data[79:0] 00000000000004ADh 00000000000004AEh AAAAAAAA000000FBh...
Page 479: Arria 10 Standard Pcs Architecture
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.2.2.10.5. Basic Mode In Basic mode, the RX FIFO operates as an elastic buffer, where buffer depths can vary. This mode allows driving write and read side of RX FIFO with different clock frequencies.
Page 480: Transmitter Datapath
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 252. Standard PCS Datapath Diagram Transmitter PMA Transmitter Standard PCS FPGA Fabric PRBS tx_coreclkin Generator tx_clkout /2, /4 tx_clkout tx_pma_div_clkout Receiver PMA Receiver Standard PCS rx_coreclkin Parallel Clock (Recovered) rx_clkout...
Page 481: Byte Serializer
32 5.3.1.2.1. Bonded Byte Serializer The bonded byte serializer is available in Arria 10 devices, and is used in applications such as PIPE, CPRI, and custom applications where multiple channels are grouped together. The bonded byte serializer is implemented by bonding all the control signals to prevent skew induction between channels during byte serialization.
Page 482 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.3.1.2.2. Byte Serializer Disabled Mode In disabled mode, the byte serializer is bypassed. The data from the TX FIFO is directly transmitted to the 8B/10B encoder, TX Bitslip, or Serializer, depending on whether or not the 8B/10B encoder and TX Bitslip are enabled.
Page 483 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 255. 8B/10B Encoder Block Diagrams When the PCS-PMA Interface Width is 20 bits When the PCS-PMA Interface Width is 10 bits To the Serializer From the Byte Serializer To the Serializer...
Page 484 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Related Information Refer to Specifications & Additional Information for more information about 8B/10B encoder codes. 5.3.1.3.2. 8B/10B Encoder Reset Condition signal resets the 8B/10B encoder. During the reset condition, tx_digitalreset the 8B/10B encoder outputs K28.5 continuously until goes low.
Page 485: Receiver Datapath
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.3.1.3.6. 8B/10B Encoder Byte Reversal Feature Figure 258. 8B/10B Encoder Byte Reversal Feature Input Output Byte Reversal Mode Data Data (8B/10B Encoder) 15 0 The byte reversal feature is available only when the PCS-PMA interface width is 16 bits or 20 bits.
Page 486 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Depending on your PCS-PMA interface width, the word aligner can be configured in one of the following modes: • Bit slip • Manual alignment • Synchronous state machine • Deterministic latency Figure 259.
Page 487 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 signals, with the same latency as the rx_syncstatus rx_patterndetect datapath, are forwarded to the FPGA fabric to indicate the word aligner status. After receiving the first word alignment pattern after rx_std_wa_patternalign...
Page 488 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes Table 261. Word Aligner Pattern Length for Various Word Aligner Modes PCS-PMA Supported Word Supported rx_std_wa_patte rx_syncstatus rx_patterndetect Interface Aligner Modes...
Page 489 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 PCS-PMA Supported Word Supported rx_std_wa_patte rx_syncstatus rx_patterndetect Interface Aligner Modes Word Aligner behavior behavior behavior rnalign Width Pattern Lengths appears in the current word boundary. Bit slip rx_std_wa_patt has no ernalign effect on word alignment.
Page 490 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 PCS-PMA Supported Word Supported rx_std_wa_patte rx_syncstatus rx_patterndetect Interface Aligner Modes Word Aligner behavior behavior behavior rnalign Width Pattern Lengths achieve deterministic latency on the RX path for CPRI and OBSAI applications.
Page 491 Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard on page 300 • How to Implement the Basic Rate Match Protocol Using the Arria 10 Transceiver Native PHY IP Core on page 300 For more information about implementing rate match FIFO for each mode.
Page 492 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.3.2.4. 8B/10B Decoder The general functionality for the 8B/10B decoder is to take a 10-bit encoded value as input and produce an 8-bit data value and a 1-bit control value as output. In configurations with the rate match FIFO enabled, the 8B/10B decoder receives data from the rate match FIFO.
Page 493: Byte Deserializer
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.3.2.4.1. 8B/10B Decoder Control Code Encoding Figure 261. 8B/10B Decoder in Control Code Group Detection When the PCS-PMA Interface Width is 10 Bits tx_clkout datain[9:0] D3.4 D24.3 D28.5 K28.5 D15.0 D0.0 D31.5...
Page 494 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Figure 262. Byte Deserializer Block Diagram Datapath from the Byte 8B/10B Decoder, Datapath to the RX PCS FIFO Deserializer Rate Match FIFO, or Word Aligner Low speed parallel clock 5.3.2.6.1. Byte Deserializer Disabled Mode In disabled mode, the byte deserializer is bypassed.
Page 495: Arria 10 Pci Express Gen3 Pcs Architecture
8B/10B scheme used in Gen1 and Gen2. The 130-bit block contains a 2-bit sync header and a 128-bit data payload. For this reason, Arria 10 devices include a separate Gen3 PCS that supports functionality at Gen3 speeds. This PIPE interface supports the seamless switching of Data and Clock between the Gen1, Gen2, and Gen3 data rates, and provides support for PIPE 3.0 features.
Page 496: Transmitter Datapath
For more information about PCIe Gen1, Gen2, and Gen3 implementation and configuration, refer to "Supported PIPE Features." • Intel Arria 10 Hard IP for PCIe IP Cores 5.4.1. Transmitter Datapath This section describes the TX FIFO and the Gearbox of the Gen3 PCS transmitter.
Page 497: Receiver Datapath
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 5.4.1.2. Gearbox The PCIe 3.0 base specification specifies a block size of 130 bits, with the exception of the SKP Ordered Sets, which can be of variable length. An implementation of a 130-bit data path takes significant resources, so the PCIe Gen3 PCS data path is implemented as 32-bits wide.
Page 498: Pipe Interface
5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 The PCI Express 3.0 base specification defines that the SKP Ordered Set (OS) can be 66, 98, 130, 162, or 194 bits long. The SKP OS has the following fixed bits: 2-bit Sync, 8-bit SKP END, and a 24-bit LFSR = 34 Bits.
Page 499: Intel Arria 10 Transceiver Phy Architecture Revision History
• Updated the configuration methods for the CTLE,and DFE schemes in the Arria 10 PMA Architecture section. • Removed a signal in the "Gen3 PCS Block Diagram" in the Arria 10 PCI Express Architecture section. 2015.12.18 Made the following changes: •...
Page 500 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Document Changes Version Made the following changes to the Standard PCS Architecture section: • Updated the Byte Serializer section for Serialize x2 and x4 modes. • Added new figures for 8B/10B Encoder Bit and Byte Reversal features.
Page 501 5. Arria 10 Transceiver PHY Architecture UG-01143 | 2018.06.15 Document Changes Version Made the following changes to the PMA Architecture section: • Added 2nd post-tap and pre-tap Pre-Emphasis signals . • Updated DFE and CTLE modes of operation and Use Models.
Page 502: Reconfiguration Interface And Dynamic Reconfiguration
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 503: Reconfiguring Channel And Pll Blocks
UG-01143 | 2018.06.15 6.1. Reconfiguring Channel and PLL Blocks The following table lists some of the available dynamic reconfiguration features in Arria 10 devices. Table 262. Arria 10 Dynamic Reconfiguration Feature Support Reconfiguration Features Channel Reconfiguration PMA analog features •...
Page 504 6. Reconfiguration Interface and Dynamic Reconfiguration UG-01143 | 2018.06.15 Figure 266. Reconfiguration Interface in Arria 10 Transceiver IP Cores Native PHY IP Core Ch0: Avalon Reconfiguration Interface Avalon-MM Master Ch1: Avalon Reconfiguration Embedded Controller in FPGA Interface or Embedded Processor on PCB...
Page 505: Reading From The Reconfiguration Interface
When two or more features share the same reconfiguration address, one feature's data bits are interleaved with another feature's data bits. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 506: Configuration Files
535 6.3. Configuration Files The Arria 10 Transceiver Native PHY and Transmit PLL IP cores optionally allow you to save the parameters you specify for the IP instances as configuration files. The configuration file stores addresses and data values for that specific IP instance.
Page 507 Bit Position Description [25:16] DPRIO address. Refer to Intel Arria 10 Transceiver Register Map for details of the address. [15:8] The channel or PLL bit mask. The bit mask exposes the bits that are configured in either the Transceiver Native PHY or the transmit PLL IP cores.
Page 508 You can generate the base and modified configuration files in the same or different folders. If you use the same folder, each configuration name must be unique. Intel recommends following the flow described in the Steps to Perform Dynamic Reconfiguration section when performing dynamic reconfiguration of either the Native PHY IP core or transmit PLL IP core.
Page 509: Multiple Reconfiguration Profiles
Analog Parameter Settings on page 585 • Arria 10 Transceiver Register Map 6.4. Multiple Reconfiguration Profiles You can optionally enable multiple configurations or profiles in the same Native PHY IP or ATX PLL IP core Parameter Editor (or both) for performing dynamic reconfiguration.
Page 510: Embedded Reconfiguration Streamer
IP guided reconfiguration flow with embedded streamer enabled. To perform a reference clock switching, use the reconfiguration flow for special cases described in Steps to Perform Dynamic Reconfiguration. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 511 Binary encoding of the n profile mapped Reconfiguration configuration Profile to select Streamer stream rcfg_busy Busy Status 1'b1 Embedded Bit is set to: Reconfiguration • 1'b1—streaming is in Streamer progress • 1'b0—streaming is complete ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 512: Arbitration
• Steps to Perform Dynamic Reconfiguration on page 516 • Analog Parameter Settings on page 585 6.6. Arbitration Figure 270. Arria 10 ATX PLL with Embedded Streamer Arria 10 ATX PLL IP Arria 10 ATX PLL Internal Configuration To/From Configuration...
Page 513 6. Reconfiguration Interface and Dynamic Reconfiguration UG-01143 | 2018.06.15 Figure 271. Arria 10 Native PHY with Embedded Streamer Arria 10 Native PHY Arria 10 Transceiver Internal Configuration Channel To/From Configuration PreSICE Registers Avalon-MM Reconfiguration Interface User Interface Reconfiguration Logic Streamer...
Page 514 6. Reconfiguration Interface and Dynamic Reconfiguration UG-01143 | 2018.06.15 In Arria 10 devices, there are two levels of arbitration: • Reconfiguration interface arbitration with the PreSICE calibration engine When you have control over the internal configuration bus, refer to the second level of arbitration: Arbitration between multiple masters within the Native PHY/PLL IPs.
Page 515: Recommendations For Dynamic Reconfiguration
When performing reconfiguration on channels not involving data rate or protocol mode change, Intel recommends that you hold the channel receiver (digital only) in reset during reconfiguration. Refer to the Arria 10 Transceiver Register Map for detailed information about the soft registers for PLL powerdown. Related Information •...
Page 516: Steps To Perform Dynamic Reconfiguration
• PLLs and Clock Networks on page 347 • Arria 10 Transceiver Register Map 6.8. Steps to Perform Dynamic Reconfiguration You can dynamically reconfigure blocks in the transceiver channel or PLL through the reconfiguration interface. The following procedure shows the steps required to reconfigure the channel and PLL blocks.
Page 517 11. Release the channel analog resets. For details about placing the channel in reset, refer to "Model 1: Default Model" and "Model 2: Acknowledgment Model" in the Resetting Transceiver Channels chapter. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 518 Reconfiguration Flow for Special Cases on page 521 • Changing PMA Analog Parameters on page 527 • Calibration on page 567 • Arbitration on page 512 • Arria 10 Transceiver Register Map ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 519: Direct Reconfiguration Flow
Calibration on page 567 • Arria 10 Transceiver Register Map 6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow Use the Native PHY IP core or PLL IP core guided reconfiguration flow to perform dynamic reconfiguration when you need to change multiple parameters or parameters in multiple addresses for the transceiver channel or PLL.
Page 520 Streaming Busy Bit Is Low Busy Bit Busy Bit Is High Related Information • Arbitration on page 512 • Changing PMA Analog Parameters on page 527 • Steps to Perform Dynamic Reconfiguration on page 516 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 521: Reconfiguration Flow For Special Cases
Before initiating the PLL switch procedure, ensure that your Transceiver Native PHY instance defines more than one transmitter PLL input. Specify the Number of TX PLL clock inputs per channel parameter on the TX PMA tab during Transceiver Native PHY parameterization. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 522 3. Encode the 4-bit value read in the previous step into an 8-bit value according to the following table: Table 268. Logical PLL Encoding 4-bit Logical PLL Bits 8-bit Mapping to Address 0x111 [3..0] {~logical_PLL_offset_readdata[3], logical_PLL_offset_readdata[1:0],logical_PLL_offset_readdata[3], logical_PLL_offset_readdata[3:0] } [7..4] {~logical_PLL_offset_readdata[7], logical_PLL_offset_readdata[5:4],logical_PLL_offset_readdata[7], logical_PLL_offset_readdata[7:4] } ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 523: Switching Reference Clocks
0x117 (Lookup Register) [7:0] Represents logical . Lookup register pll_refclk4 refclk4 stores the mapping from logical x117[7:0] to the physical refclk. refclk4 ATX refclk selection MUX. 0x112 [7:0] ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 524 MUX_0. refclk3 0x11B (Lookup Register) [7:0] Represents logical . Lookup pll_refclk4 refclk4 MUX_0 register stores the mapping from logical x11B[7:0] to the physical refclk for MUX_0. refclk4 continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 525 Read from 0x118[7:0] • Write the value from 0x118 [7:0] to 0x114 [7:0] 2. Modify MUX_1 value: • Read from 0x11E [7:0] • Write the value read from 0x11E [7:0] to 0x11C [7:0] ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 526 0x16C (Lookup Register) [7:0] Represents logical cdr_refclk2 refclk2 Lookup register x16C[7:0] stores the mapping from logical to the physical refclk. refclk2 continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 527: Changing Pma Analog Parameters
Steps to Perform Dynamic Reconfiguration on page 516 6.12. Changing PMA Analog Parameters You can use the reconfiguration interface on the Transceiver Native PHY IP core to change the value of PMA analog features. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 528 RMWs using direct reconfiguration flow Table 272. PMA Analog Settings that are Channel or System Dependent PMA Analog Feature Fitter Report Name Arria 10 Transceiver Register Map Attribute Name vod_output_swing_ctrl vod_output_swing_ctrl Pre-emphasis pre_emp_sign_1st_post_tap...
Page 529 — Examples: Slew rate, Equalizer Bandwidth, Compensation Enable Table 273. PMA Analog Settings that are Device Dependent PMA Analog Feature Fitter Report Name Arria 10 Transceiver Register Map Attribute Name Slew Rate (TX Buffer) Slew_rate_ctrl Slew_rate_ctrl Equalizer Bandwidth...
Page 530: Changing Vod, Pre-Emphasis Using Direct Reconfiguration Flow
1st post-tap, read and store the value of address 0x105. 3. Select a valid value for the feature according to the Arria 10 register map. For example, a valid setting for pre-emphasis 1st post-tap has a bit encoding of 5'b00001.
Page 531: Changing Ctle Settings In Manual Mode Using Direct Reconfiguration Flow
CTLE AC gain in high gain mode, read and store the value of address 0x167[5:1]. 3. Select a valid value for the feature according to the Arria 10 register map. For example, a valid setting for CTLE AC Gain has a bit encoding of 5’b00000.
Page 532 0x124 Enable DFT 1'b1 0x11F Eq_bw_sel 2'b01 (Gen3) 2'b00 (Gen1/2) Refer to the "Arria 10 Register Map" and "Arria 10 Adaptation Tool" for details on adaptation registers. Related Information • How to Enable CTLE and DFE on page 456 •...
Page 533: Enabling And Disabling Loopback Modes Using Direct Reconfiguration Flow
6. Reconfiguration Interface and Dynamic Reconfiguration UG-01143 | 2018.06.15 6.12.4. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow Arria 10 devices have three loopback modes: • Serial Loopback • Reverse Serial Loopback (Pre-CDR) • Reverse Serial Loopback (Post-CDR) The loopback mode can be dynamically reconfigured by accessing the register space.
Page 534 In the post-CDR mode, received data passes through the RX CDR and then loops back to the TX output buffer. Perform read-modify-write to the following registers to enable this mode. Figure 275. Reverse Serial Loopback Mode (Post-CDR) Transmitter Serializer Post-CDR Reverse Receiver Serial Loopback Deserializer ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 535: Ports And Parameters
1. The following figure shows the signals available when the Native PHY IP core is configured for four channels and the Share reconfiguration interface option is enabled. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 536 1, corresponds to the reconfig_address[29:20] reconfiguration address bus of logical channel 2, and reconfig_address[39:30] correspond to the reconfiguration address bus of logical channel 3. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 537 The behavior of this signal depends on whether the feature Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE is enabled or not. For more details, refer to the Arbitration section. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 538 On / Off Available in Native PHY and TX PLL IP parameter editors. Creates a C header file that contains the current configuration data values for all reconfiguration addresses. Disabled by default. continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 539 Store configuration to selected profile buttons in sequence. This operation loads the parameter settings from stored profile specified by the Selected reconfiguration profile parameter and then stores the parameters back to the profile. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 540 Parameter Editor, if one or more of the individual TX pin swing settings need to be changed, then enable the option to override the Intel- recommended defaults to individually modify the settings. For details about QSF assignments for the analog settings, refer to the Analog Parameter Settings chapter.
Page 541 Analog Parameter Settings on page 585 • Embedded Debug Features on page 544 • Arbitration on page 512 • Changing PMA Analog Parameters on page 527 • Calibration on page 567 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 542: Dynamic Reconfiguration Interface Merging Across Multiple Ip Blocks
The Native PHY provides the ability to create channels that are either simplex or duplex instances. However, each physical transceiver channel in Arria 10 devices is fully duplex. You can share the reconfiguration interfaces across different IP blocks by manually making a QSF assignment.
Page 543 These instances are assigned to reconfiguration group For Native PHY 0—transmit-only instance: set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to tx[0] (62) Please refer to Calibration section on how to calibrate when those features are not available. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 544: Embedded Debug Features
For details on TTK usage refer to "Debugging Transceiver Links" in Quartus Prime Standard Edition Handbook Volume 3: Verification. The Arria 10 Transceiver Native PHY, ATX PLL, fPLL, and CMU PLL IP cores provide the following optional debug features to facilitate embedded test and debug capability: •...
Page 545 Control and status registers are optional registers that memory-map some of the status outputs from and control inputs to the Native PHY and PLL. The following control and status registers are available for the Native PHY IP core. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 546 1’b1 indicates the rx_is_lockedtodata receiver is locked to the incoming data. 0x280[1] Shows the status of the current channel’s rx_is_lockedtoref signal. 1’b1 indicates the rx_is_lockedtoref receiver is locked to the reference clock. continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 547 Enable PRBS Soft Accumulators option in the Native PHY IP Parameter Editor. The PRBS soft accumulator has three control bits (Enable, Reset, and Snapshot) and one status bit (PRBS Done). ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 548 For each count, the absolute bit errors could range from one to the width of PCS-PMA interface. For more information about using the hard PRBS blocks, refer to the "Using Data Pattern Generators and Checkers" section. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 549 Note: Intel recommends that you disable the byte serializer and deserializer blocks when using the soft PRBS accumulators. When the byte serializer and deserializer blocks are enabled, the number of bits counted are halved because the clock is running at half the rate.
Page 550: Using Data Pattern Generators And Checkers
UG-01143 | 2018.06.15 6.16. Using Data Pattern Generators and Checkers The Arria 10 transceivers contain hardened data generators and checkers to provide a simple and easy way to verify and characterize high speed links. Hardening the data generators and verifiers saves FPGA fabric logic resources. The pattern generator block supports the following patterns: •...
Page 551 Bit Addresses Encoding Encoding Address (HEX) 0x006 [2:0] tx_pma_data_sel prbs_pat 3'b100 Select PRBS Generator Block prbs9_dwidth prbs9_10b 1'b1 Enable PRBS9 in 10-bit mode prbs9_64b 1'b0 Enable PRBS9 in 64-bit mode continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 552 You must read and save the value in the register 0x111[5:0] before changing the setting to xN non bonding. To disable the PRBS generator, write the x1_clcok_source_sel original values back into the read-modify-write address. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 553 6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration. To disable the PRBS generator, write the original values back into the read-modify- write addresses in Register Map for PRBS Generators for bonded and non bonded designs. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 554 You must perform a sequence of read-modify-writes to addresses 0x006, 0x007, 0x008, and 0x110, 0x111and to enable either the PRBS data generator in bonded designs. To enable either the PRBS data generator, follow these steps: ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 555 7. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration. Note: A dash (-) indicates that the corresponding bit value should not be modified during read-modify-write. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 556 6. Perform the necessary steps from steps 9 to 12 in Steps to Perform Dynamic Reconfiguration. To disable the PRBS verifier write the original values back into the read-modify- write addresses listed above. Related Information Steps to Perform Dynamic Reconfiguration on page 516 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 557 You must perform a sequence of read-modify-writes to addresses 0x00A, 0x00B, 0x00C, 0x13F, 0x111 and to enable the PRBS data checker in bonded designs. To enable the PRBS checker, follow these steps: ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 558 Address (HEX) tx_static_polarity_inversion 1'b1 Disables PRBS inversion 1'b0 Enables PRBS inversion (default) rx_static_polarity_inversion 1'b1 Disables PRBS inversion 1'b0 Enables PRBS inversion (default) Related Information Steps to Perform Dynamic Reconfiguration on page 516 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 559: Using Pseudo Random Pattern Mode
UG-01143 | 2018.06.15 6.16.2. Using Pseudo Random Pattern Mode You can use the Arria 10 Pseudo Random Pattern (PRP) generator and verifier in the scrambler and descrambler to generate random data pattern and seed that the scrambler can use. PRP mode is a test mode of the scrambler. Two seeds are available to seed the scrambler: all 0s or two local fault-ordered sets.
Page 560: Timing Closure Recommendations
516 6.17. Timing Closure Recommendations Intel recommends that you enable the multiple reconfiguration profiles feature in the Native PHY IP core if any of the modified or target configurations involve changes to PCS settings. Using multiple reconfiguration profiles is optional if the reconfiguration involves changes to only PMA settings such as PLL switching, CGB divider switching, and refclk switching.
Page 561 Gbps, PCS-PMA width = 64) and drives core logic B in the FPGA fabric. Figure 280. Using Multiple Reconfiguration Profiles Transceiver Channel Transmitter (TX) FPGA Fabric tx_clkout Core Logic (A) for Standard Receiver (RX) Core Logic (B) for Enhanced rx_clkout ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 562 Note: If any of the profile or configuration switch involves switching from FIFO to the register mode, then the false paths should be set between the PCS-PMA interface register and the core logic because the common clock point is within the PCS-PMA interface. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 563: Unsupported Features
• Serialization factor changes on bonded channels • TX PLL switching on bonded channels Note: Transceiver Native PHY IP non-bonded configuration to another Transceiver Native PHY IP non-bonded configuration is supported. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 564: Arria 10 Transceiver Register Map
PMA analog settings are governed by a set of rules. Not all combinations of V and pre-emphasis are valid. Please refer to Arria 10 Pre-Emphasis and Output Swing Settings for current valid settings. Also, refer to "Analog Parameter Settings" and setup guidelines on post_tap polarity settings."...
Page 565 Removed four tables from the "On-Die Instrumentation" section. • Changed the procedure in the "Using ODI to Build On-chip Eye Process" section. • Added entry to “Arria 10 Dynamic Reconfiguration Feature Support” table • Improved description of access requests in the “Interacting with the Reconfiguration Interface” section •...
Page 566 • Updated the introduction section of the chapter to better explain dynamic reconfiguration use cases. • Added figures Reconfiguration Interface in Arria 10 Transceiver IP Cores and Top Level Signals of the Reconfiguration Interface. • Added Timing Closure Recommendations section.
Page 567: Calibration
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 568 — Write 0x03 to offset address 0x000 [7:0], DFE adaptation triggering has to enable through 0x100[6]. • If you no longer need to use the internal reconfiguration bus: — Write 0x03 to offset address 0x000 [7:0]. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 569: Calibration Registers
Avalon Interface Specifications • Reconfiguration Interface and Dynamic Reconfiguration Chapter on page 502 7.2. Calibration Registers The Arria 10 transceiver PMA and PLLs include the following types of registers for calibration: • Avalon-MM interface arbitration registers • Calibration enable registers •...
Page 570: Transceiver Channel Calibration Registers
Fractional PLL Calibration Registers fPLL Calibration Enable Register Offset Address 0x100 Reserved fPLL calibration enable. Set 1 to enable calibration. (64) The transceiver channel, ATX PLL, and fPLL use the same offset address. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 571: Atx Pll Calibration Registers
Simplex TX and Simplex RX channel merging is involved. To merge a Simplex TX and a Simplex RX channel into one physical channel, refer to Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks on page 542. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 572 PreSICE Avalon-MM interface control. This register is available to check who controls the bus, no matter if, separate from the status reconfig_waitrequest of AVMM arbitration with PreSICE is enabled or not. 0x1: PreSICE is controlling the internal configuration bus. continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 573: Rate Switch Flag Register
If you change the line rate, it may require new charge pump settings, which are stored into the Avalon-MM reconfiguration register space. During RX PMA calibration (including CDR), PreSICE needs to know which set of CDR charge pump setting to use. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 574: Power-Up Calibration
The ATX PLL cal_busy signal goes low after the channels’ cal_busy tx_cal_busy rx_cal_busy signals. Intel recommends that you wait until all signals are low before *_cal_busy requesting any access. All power-up calibration starts from Vreg calibration for all banks and channels. ®...
Page 575 2. Wait for PCIe reference clock toggle. 3. PCIe Hard IP 0 calibration (if used). 4. PCIe Hard IP 1 calibration (if used). 5. Calibration of all non-PCIe Hard IP channels in calibration sequence. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 576: User Recalibration
Bank 1 RX PMA and TX PMA Calibration (1) CDR and CMU PLL calibration are part of RX PMA calibration. 7.4. User Recalibration User Recalibration is needed if below conditions are met: ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 577 PLL reconfiguration, and PLL and channel interface switching, then you must reset the transceivers. The proper reset sequence is required after calibration. Intel recommends you use the Transceiver PHY Reset Controller which has...
Page 578 • Implementing PLL Feedback Compensation Bonding Mode on page 405 • Implementing PLL Cascading on page 408 • Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs on page 349 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 579: Recalibration After Transceiver Reference Clock Frequency Or Data Rate Change
"Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter. 2. Proceed to the next step if fPLL is not used in your application, otherwise perform the fPLL user recalibration process: ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 580 0x281[1:0] to check status until *cal_busy calibration is complete. Related Information Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs on page 349 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 581: Calibration Example
PLL spacing guideline as stated in the "Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs" chapter. Related Information Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs on page 349 ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 582: Cdr/Cmu Pll Recalibration
*cal_busy 0x281[1:0] to check status until calibration is complete. *cal_busy Related Information Transceiver Channel Calibration Registers on page 570 For more details about PMA recalibration ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 583: Calibration Revision History
Added the "Rate Switch Flag Register" section. • Added steps to the "User Recalibration" section. • Changed the description in the "CDR/CMU PLL Recalibration" section. • Added steps to the "PMA Recalibration" section. continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 584 Changed the addresses in the "Check Calibration Status" section. • Changed "Avalon-MM interface" to "internal configuration bus" in the "PMA Recalibration" section. • Added the "Capability Registers" section. 2014.12.15 Initial release. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 585: Analog Parameter Settings
Intel's standard warranty, but reserves the right to make changes to any products and services Registered at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
Page 586: Analog Parameter Settings List
RX serial data Equalizer Fixed Tap Five Coefficient XCVR_A10_RX_ADP_DFE_FXTAP5_ Receiver Decision Feedback RX serial data Equalizer Fixed Tap Five Sign XCVR_A10_RX_ADP_DFE_FXTAP6 Receiver Decision Feedback RX serial data Equalizer Fixed Tap Six Coefficient continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 587 TX serial data Pre-emphasis D_POST_TAP Post-Tap Polarity XCVR_A10_TX_PRE_EMP_SWITCHI Transmitter Pre-Emphasis First Pre- TX serial data Pre-emphasis NG_CTRL_PRE_TAP_1T Tap Magnitude XCVR_A10_TX_PRE_EMP_SWITCHI Transmitter Pre-Emphasis Second TX serial data Pre-emphasis NG_CTRL_PRE_TAP_2T Pre-Tap Magnitude continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 588: Receiver General Analog Settings
QSF assignments XCVR_A10_RX_EQ_DC_GAIN_TRIM and XCVR_A10_RX_ADP_VGA_SEL. Table 307. Available Options Value Description SR (Short Reach) Less than or equal to10dB IL, used for Chip-to-chip communication LR (Long Reach) >10dB IL, used for Backplane communication ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 589: Xcvr_A10_Rx_Term_Sel
RX serial data pin. Syntax set_instance_assignment -name XCVR_A10_RX_LINK <value> -to <rx_serial_data pin name> Related Information Arria 10 Device Datasheet 8.4.2. XCVR_A10_RX_TERM_SEL Pin planner or Assignment Editor Name Receiver On-Chip Termination Description Controls the on-chip RX differential termination. For data rates higher than 25 Gbps, set the termination resistance to 85 Ohm.
Page 590: Receiver Analog Equalization Settings
If no assignment is made, S1_MODE is chosen by default for datarate less than or equal to 25.8 Gbps. (65) These values are for the assignment editor. For the actual values, refer to the Arria 10 Device Datasheet. ®...
Page 591 STG2_GAIN7 Equalizer DC gain setting 13 DC Gain 3 STG3_GAIN7 Equalizer DC gain setting 20 DC Gain 4 STG4_GAIN7 Equalizer DC gain setting 27 (66) Refer to Arria 10 Data Sheet ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 592 Controls the AC gain of the continuous time linear equalizer (CTLE) in high gain mode. Arria 10 transceivers support two CTLE modes, high gain mode and high data rate mode. As a default, high data rate mode is enabled for data rates up to 25.8 Gbps.
Page 593: Vga Settings
For datarate > 17.4 Gbps, default value is RADP_VGA_SEL_4. For RX_LINK = LR and CTLE mode = NON_S1_MODE: default value is RADP_VGA_SEL_4. For RX_LINK = LR and CTLE mode = S1_MODE and datarate <= 4.5Gbps: default value is RADP_VGA_SEL_4. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 594: Decision Feedback Equalizer (Dfe) Settings
0. DFE tap1 in the only tap which is always positive and hence there is no QSF assignment for DFE tap1 sign bit. Other taps can be positive or negative. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 595 0 or 1 Sign 0 = Positive and 1=Negative XCVR_A10_RX_ADP_DFE_FX Receiver Decision Feedback RADP_DFE_FXTAP9_<0 to DFE fixed tap 9 Coefficient TAP9 Equalizer Fixed Tap Nine 63> Setting <0 to 63> Coefficient continued... ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 596: Transmitter General Analog Settings
10dB and value LR is used for link insertion loss greater than 10dB. If this QSF assignment is not done, Quartus Prime assigns SR as the default value. This is used for data rate legality check during compilation. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 597: Xcvr_A10_Tx_Term_Sel
> 10dB IL, used for Backplane communication Note: The maximum data rate supported by transceiver channels depends on the device speed grade, power mode, and the type of transceiver channel. Refer to Arria 10 Device Datasheet for more details. Assign To TX serial data pin.
Page 598: Xcvr_Vccr_Vcct_Voltage - Tx
VCCR_GXB or VCCT_GXB voltage 1_0V VCCR_GXB or VCCT_GXB voltage 0_9V VCCR_GXB or VCCT_GXB voltage (67) These are assignment editor values. For the actual values, refer to the Arria 10 Device Datasheet. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 599: Xcvr_A10_Tx_Slew_Rate_Ctrl
TX serial data pin. Syntax set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE <value> -to <tx_serial_data pin name> Related Information Arria 10 Device Datasheet 8.6.5. XCVR_A10_TX_SLEW_RATE_CTRL Pin planner or Assignment Editor Name Transmitter Slew Rate Control Description Specifies the slew rate of the output signal. The valid values span from the slowest rate to the fastest rate.
Page 600: Transmitter Pre-Emphasis Analog Settings
<value> -to <tx_serial_data pin name> 8.7.2. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T Pin Planner or Assignment Editor Name Transmitter Pre-Emphasis Second Pre-Tap Polarity Description Controls the polarity of the second pre-tap for pre-emphasis. The default value is FIR_PRE_2T_NEG. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 601: Xcvr_A10_Tx_Pre_Emp_Sign_1St_Post_Tap
XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP <value> -to <tx_serial_data pin name> 8.7.4. XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP Pin planner or Assignment Editor Name Transmitter Pre-Emphasis Second Post-Tap Polarity Description Controls the polarity of the second post-tap for pre-emphasis. The default value is FIR_POST_2T_NEG. ® ® Intel Arria 10 Transceiver PHY User Guide...
Page 602: Xcvr_A10_Tx_Pre_Emp_Switching_Ctrl_Pre_Tap_1T
Available Options Value Description 0 – 16 Magnitude 0 – 16 Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings. Assign To TX serial data pin. Syntax set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T <value>...
Page 603: Xcvr_A10_Tx_Pre_Emp_Switching_Ctrl_1St_Post_Tap
Available Options Value Description 0 – 7 Magnitude 0 – 7 Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings. Assign To TX serial data pin. Syntax set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T <value>...
Page 604: Xcvr_A10_Tx_Pre_Emp_Switching_Ctrl_2Nd_Post_Tap
Available Options Value Description 0 – 12 Magnitude 0 – 12 Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings. Assign To TX serial data. Syntax set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP <value> -to <tx_serial_data pin name>...
Page 605: Dedicated Reference Clock Settings
Available Options Value Description 0 – 31 Magnitude 0 – 31 Note: Refer to Arria 10 Pre-Emphasis and Output Swing Settings spreadsheet for selecting legal pre-emphasis and differential output voltage settings. Assign To TX serial data pin. Syntax set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL <value>...
Page 606: Xcvr_A10_Tx_Xtx_Path_Analog_Mode
Updated that "DFE continuous mode" is not supported any more. DFE is supported in three modes- Disabled, Manual, Adaptation Enabled. • Changed the "Arria 10 Register Map” for available DFE modes, CTLE and VGA modes. • Changed the maximum supported data rate for GT devices to 25.8 G.
Page 607 Made the following changes: • Modified the Rules section for XCVR_A10_TX_COMPENSATION_EN. • Changed Available Options for XCVR_A10_RX_ONE_STAGE_ENABLE parameter settings table. • Changed the "XCVR_A10_RX_ADP_CTLE_ACGAIN_4S" parameter setting. • Added "XCVR_VCCR_VCCT_VOLTAGE" parameter setting. 2014.08.15 Initial release. ® ® Intel Arria 10 Transceiver PHY User Guide...

Intel Arria 10 User Manual

1 Arria ® 10 Transceiver PHY Overview

2 Implementing Protocols in Arria 10 Transceivers

3 Plls and Clock Networks

4 Resetting Transceiver Channels

5 Arria 10 Transceiver PHY Architecture

6 Reconfiguration Interface and Dynamic Reconfiguration

7 Calibration

8 Analog Parameter Settings

Quick Links

User Guide

Related Manuals for Intel Arria 10

Summary of Contents for Intel Arria 10