Design Limitation; Intel Fpga Hdmi Design Example Parameters - Intel Arria 10 series User Manual

1.6 Design Limitation

You may encounter timing violation on the maximum skew constraints required for the
designs that use TX PMA and PCS bonding.
Choose the transceiver channels farther away from the Hard IP (HIP) block to meet
the maximum skew tolerance constraints requirement.

1.7 Intel FPGA HDMI Design Example Parameters

Table 5. Intel FPGA HDMI Design Example Parameters for Intel Arria 10 Devices
These options are available for Intel Arria 10 devices only.
Parameter
Select Design
Simulation
Synthesis
Generate File Format
Select Board
Change Target Device
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Intel FPGA HDMI Design Example User Guide for Intel
10
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1 Intel FPGA HDMI Design Example Quick Start Guide for Intel
Value
Available Design Example
Arria 10 HDMI RX-TX Select the design example to be generated. The generated design
Retransmit example has preconfigured parameter settings. It does not follow user
settings.
Design Example Files
On, Off Turn on this option to generate the necessary files for the simulation
testbench.
On, Off Turn on this option to generate the necessary files for Intel Quartus
Prime compilation and hardware demonstration.
Generated HDL Format
Verilog, VHDL Select your preferred HDL format for the generated design example
fileset.
Note: This option only determines the format for the generated top
Target Development Kit
No Development Kit, Select the board for the targeted design example.
Arria 10 GX FPGA
• No Development Kit: This option excludes all hardware aspects for
Development Kit,
the design example. The IP core sets all pin assignments to virtual
Custom Development
pins.
Kit
• Arria 10 GX FPGA Development Kit: This option automatically selects
the project's target device to match the device on this development
kit. You may change the target device using the Change Target
Device parameter if your board revision has a different device
variant. The IP core sets all pin assignments according to the
development kit.
• Custom Development Kit: This option allows the design example to
be tested on a third party development kit with an Intel FPGA. You
may need to set the pin assignments on your own.
Target Device
On, Off Turn on this option and select the preferred device variant for the
development kit.
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Arria 10 Devices
Description
level IP files. All other files (e.g. example testbenches and top
level files for hardware demonstration) are in Verilog HDL format.
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Arria 10 Devices
UG-20077 | 2017.11.06