Combining Status Or Pll Lock Signals - Intel Arria 10 User Manual

Figure 217. User-Coded Reset Controller, Transceiver PHY, and TX PLL Interaction
clock
Table 250. User-coded Reset Controller, Transceiver PHY, and TX PLL Signals
Signal Name
pll_powerdown
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
clock
pll_cal_busy
pll_locked
tx_cal_busy
rx_is_lockedtodata
rx_cal_busy
rx_is_lockedtoref

4.6. Combining Status or PLL Lock Signals

You can combine multiple PHY status signals before feeding into the reset controller as
shown below.
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Intel Arria 10 Transceiver PHY User Guide
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tx_analogreset
User-Coded
tx_digitalreset
Reset
rx_analogreset
Controller
rx_digitalreset
tx_cal_busy
rx_cal_busy
rx_is_lockedtoref
rx_is_lockedtodata
You can logical OR the pll_cal_busy
and tx_cal_busy signals.
Transmit
PLL
Direction
Output Resets the TX PLL when asserted high.
Output Resets the TX PMA when asserted high.
Output Resets the TX PCS when asserted high.
Output Resets the RX PMA when asserted high.
Output Resets the RX PCS when asserted high.
Input Clock signal for the user-coded reset controller. You can use the system
clock without synchronizing it to the PHY parallel clock. The upper limit on
the input clock frequency is the frequency achieved in timing closure.
Input A high on this signal indicates the PLL is being calibrated.
Input A high on this signal indicates that the TX PLL is locked to the ref clock.
Input A high on this signal indicates that TX calibration is active. If you have
multiple PLLs, you can OR their
Input A high on this signal indicates that the RX CDR is in the lock-to-data (LTD)
mode.
Input A high on this signal indicates that RX calibration is active.
Input A high on this signal indicates that the RX CDR is in the lock-to-reference
(LTR) mode. This signal may toggle or be deasserted when the CDR is in
LTD mode.
4. Resetting Transceiver Channels
UG-01143 | 2018.06.15
Transceiver PHY Instance
Transmitter
Transmitter
PCS
Receiver
Receiver
PCS
Description
signals together.
pll_cal_busy
PMA
PMA